LM3S2965 Datasheet, PDF (162/542 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Input/Outputs (GPIOs)
9.1.1.2
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 168) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 9-1 on page 162, where u is data unchanged by the write.
Figure 9-1. GPIODATA Write Example
ADDR[9:2] 9 8 7 6 5 4 3 2 1 0
0x098 0 0 1 0 0 1 1 0 1 0
0xEB 1 1 1 0 1 0 1 1
GPIODATA u u 1 u u 0 1 u
76543210
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-2 on page 162.
Figure 9-2. GPIODATA Read Example
ADDR[9:2] 9 8 7 6 5 4 3 2 1 0
0x0C4 0 0 1 1 0 0 0 1 0 0
GPIODATA 1 0 1 1 1 1 1 0
9.1.2
Returned Value 0 0 1 1 0 0 0 0
76543210
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
162
June 04, 2007
Preliminary