LM3S2965 Datasheet, PDF (478/542 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; a 0 bit indicates that the event in question has not occurred. These are R/W1C
registers; writing a 1 to a bit position clears the corresponding interrupt reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
4
3
2
1
0
Name
reserved
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
IntCntLoad
IntCntZero
Type
RO
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Indicates that the counter has matched the comparator B value while
counting down.
Indicates that the counter has matched the comparator B value while
counting up.
Indicates that the counter has matched the comparator A value while
counting down.
Indicates that the counter has matched the comparator A value while
counting up.
Indicates that the counter has matched the PWMnLOAD register.
Indicates that the counter has matched 0.
478
June 04, 2007
Preliminary