LM3S2965 Datasheet, PDF (17/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 343
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 345
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 347
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 348
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 349
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 350
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 351
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 352
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 353
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 354
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 355
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 356
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 357
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 358
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 359
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 360
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 361
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 362
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 363
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 364
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 365
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 366
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 380
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 381
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 385
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 386
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 387
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 388
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 389
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 390
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 391
Register 10: I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 393
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 394
Register 12: I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 396
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 397
Register 14: I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 398
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 399
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 400
CAN ............................................................................................................................................... 401
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 415
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 417
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 420
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 421
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 423
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 424
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 426
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 427
June 04, 2007
17
Preliminary