LM3S2965 Datasheet, PDF (13/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
List of Registers
System Control .............................................................................................................................. 60
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 68
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 70
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 71
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 72
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 73
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 74
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 75
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 76
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 80
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 81
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 83
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 84
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 86
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 87
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 89
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 91
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 93
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 96
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 98
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 103
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 106
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 109
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 111
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 113
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 115
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 116
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 118
Hibernation Module ..................................................................................................................... 119
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 125
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 126
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 127
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 128
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 129
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 131
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 132
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 133
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 134
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 135
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 136
Internal Memory ........................................................................................................................... 137
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 142
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 143
June 04, 2007
13
Preliminary