LM3S2965 Datasheet, PDF (19/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 472
PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 473
PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 474
PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 474
PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 474
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 475
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 475
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 475
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 477
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 477
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 477
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 478
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 478
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 478
PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 479
PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 479
PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 479
PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 480
PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 480
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 480
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 481
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 481
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 481
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 482
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 482
PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 482
PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 483
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 483
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 483
PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 485
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 485
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 485
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 486
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................ 486
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 486
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 487
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 487
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 487
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 488
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 488
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 488
QEI ................................................................................................................................................. 489
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 494
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 496
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 497
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 498
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 499
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 500
June 04, 2007
19
Preliminary