LM3S2965 Datasheet, PDF (43/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
3 Memory Map
The memory map for the LM3S2965 controller is provided in Table 3-1 on page 43.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Note: In Table 3-1 on page 43 addresses not listed are reserved.
Table 3-1. Memory Map^a
Start
End
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.1000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.9000
0x4000.A000
0x4000.C000
0x4000.D000
0x4000.E000
0x4000.F000
0x4001.0000
Peripherals
0x4002.0000
0x4002.0800
0x4002.1000
0x4001.1800
0x4002.2000
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.7000
0x1FFF.FFFF
0x200F.FFFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.3FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.9FFF
0x4000.BFFF
0x4000.CFFF
0x4000.DFFF
0x4000.EFFF
0x4000.FFFF
0x4001.FFFF
0x4002.07FF
0x4002.0FFF
0x4002.17FF
0x4002.1FFF
0x4002.3FFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.7FFF
Description
For details
on
registers,
see page ...
On-chip flash ^b
141
Bit-banded on-chip SRAM ^c
141
Reserved non-bit-banded SRAM space
-
Bit-band alias of 0x2000.0000 through 0x200F.FFFF 137
Reserved non-bit-banded SRAM space
-
Watchdog timer
237
Reserved
-
GPIO Port A
167
GPIO Port B
167
GPIO Port C
167
GPIO Port D
167
SSI0
342
SSI1
342
Reserved
-
UART0
298
UART1
298
UART2
298
Reserved
-
Reserved for future FiRM peripherals
-
I2C Master 0
379
I2C Slave 0
392
I2C Master 1
379
I2C Slave 1
392
Reserved
-
GPIO Port E
167
GPIO Port F
167
GPIO Port G
167
GPIO Port H
167
June 04, 2007
43
Preliminary