LM3S2965 Datasheet, PDF (67/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
Offset Name
Type
Reset
Description
0x034 LDOPCTL
0x040 SRCR0
0x044 SRCR1
0x048 SRCR2
0x050 RIS
0x054 IMC
0x058 MISC
0x05C RESC
0x060 RCC
0x064 PLLCFG
0x070 RCC2
0x100 RCGC0
0x104 RCGC1
0x108 RCGC2
0x110 SCGC0
0x114 SCGC1
0x118 SCGC2
0x120 DCGC0
0x124 DCGC1
0x128 DCGC2
0x144 DSLPCLKCFG
R/W
R/W
R/W
R/W
RO
R/W
R/W1C
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000.0000
0x00000000
0x00000000
0x00000000
0x0000.0000
0x0000.0000
0x0000.0000
-
0x07AE.3AD1
-
0x0780.2800
0x00000040
0x00000000
0x00000000
0x00000040
0x00000000
0x00000000
0x00000040
0x00000000
0x00000000
0x0780.0000
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL Translation
Run-Mode Clock Configuration 2
Run Mode Clock Gating Control Register 0
Run Mode Clock Gating Control Register 1
Run Mode Clock Gating Control Register 2
Sleep Mode Clock Gating Control Register 0
Sleep Mode Clock Gating Control Register 1
Sleep Mode Clock Gating Control Register 2
Deep Sleep Mode Clock Gating Control Register 0
Deep Sleep Mode Clock Gating Control Register 1
Deep Sleep Mode Clock Gating Control Register 2
Deep Sleep Clock Configuration
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
71
115
116
118
72
73
74
75
76
80
81
94
100
109
96
103
111
98
106
113
83
June 04, 2007
67
Preliminary