LM3S2965 Datasheet, PDF (341/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x00000000.
3. Write the SSICPSR register with a value of 0x00000002.
4. Write the SSICR0 register with a value of 0x000009C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
14.4
Register Map
“Register Map” on page 341 lists the SSI registers. The offset listed is a hexadecimal increment to
the register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 14-1. SSI Register Map
Offset Name
Type
0x000 SSICR0
R/W
0x004 SSICR1
R/W
0x008 SSIDR
R/W
0x00C SSISR
RO
0x010 SSICPSR
R/W
0x014 SSIIM
R/W
0x018 SSIRIS
RO
0x01C SSIMIS
RO
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
0x0000.0000
Description
SSI Control 0
SSI Control 1
SSI Data
SSI Status
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
SSI Masked Interrupt Status
See
page
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352
June 04, 2007
341
Preliminary