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LM3S2965 Datasheet, PDF (24/542 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
â Hardware-division and single-cycle-multiplication
â Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
â 42 interrupts with eight priority levels
â Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
â Unaligned data access, enabling data to be efficiently packed into memory
â Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
â Internal Memory
â 256 KB single-cycle flash
⢠User-managed flash block protection on a 2-KB block basis
⢠User-managed flash data programming
⢠User-defined and managed flash-protection block
â 64 KB single-cycle SRAM
â General-Purpose Timers
â Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timer/counters. Each GPTM can be configured to operate independently as timers or event
counters (eight total): as a single 32-bit timer (four total), as one 32-bit Real-Time Clock (RTC)
to event capture, for Pulse Width Modulation (PWM), or to trigger analog-to-digital conversions
â 32-bit Timer modes
⢠Programmable one-shot timer
⢠Programmable periodic timer
⢠Real-Time Clock when using an external 32.768-KHz clock as the input
⢠User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
⢠ADC event trigger
â 16-bit Timer modes
⢠General-purpose timer function with an 8-bit prescaler
⢠Programmable one-shot timer
⢠Programmable periodic timer
⢠User-enabled stalling when the controller asserts CPU Halt flag during debug
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June 04, 2007
Preliminary
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