LM3S2965 Datasheet, PDF (456/542 Pages) List of Unclassifed Manufacturers – Microcontroller

Analog Comparators
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
31
30
29
28
27
Type RO
Reset
0
15
Type RO
Reset
0
RO
RO
0
0
14
13
reserved
RO
RO
0
0
RO
RO
0
0
12
11
TOEN
RO
R/W
0
0
26
25
24
23
22
21
reserved
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
10
9
ASRCP
R/W
R/W
0
0
8
7
reserved TSLVAL
RO
R/W
0
0
6
5
TSEN
R/W
R/W
0
0
20
RO
0
4
ISLVAL
R/W
0
19
18
RO
RO
0
0
3
2
ISEN
R/W
R/W
0
0
17
16
RO
RO
0
0
1
0
CINV reserved
R/W
RO
0
0
Bit/Field
31:12
11
10:9
Name
reserved
TOEN
ASRCP
Type
RO
R/W
R/W
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
ASRCP Function
00
Pin value
01
Pin value of C0+
10
Internal voltage reference
11
Reserved
8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TSLVAL
R/W
0
The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.
456
June 04, 2007
Preliminary