LM3S2965 Datasheet, PDF (485/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
These registers control the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These
events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal;
and PWM2GENB, the PWM2B signal.
Each field in these registers can take on one of the values defined in Table 18-2 on page 484, which
defines the effect of the event on the output signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
Type RO
Reset
0
15
Type RO
Reset
0
RO
RO
0
0
14
13
reserved
RO
RO
0
0
RO
RO
RO
0
0
0
12
11
10
ActCmpBD
RO
R/W
R/W
0
0
0
25
24
23
22
reserved
RO
RO
RO
RO
0
0
0
0
9
8
ActCmpBU
R/W
R/W
0
0
7
6
ActCmpAD
R/W
R/W
0
0
21
20
RO
RO
0
0
5
4
ActCmpAU
R/W
R/W
0
0
19
18
RO
RO
0
0
3
2
ActLoad
R/W
R/W
0
0
17
16
RO
RO
0
0
1
0
ActZero
R/W
R/W
0
0
Bit/Field
31:12
11:10
9:8
7:6
5:4
3:2
1:0
Name
reserved
ActCmpBD
ActCmpBU
ActCmpAD
ActCmpAU
ActLoad
ActZero
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The action to be taken when the counter matches comparator B while
counting down.
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 474) is set to 1.
The action to be taken when the counter matches comparator A while
counting down.
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The action to be taken when the counter matches the load value.
The action to be taken when the counter is 0.
June 04, 2007
485
Preliminary