S-7600A Datasheet, PDF (51/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
9. Reset Functions
9.1. Overview
The S-7600A has two reset functions which are hardware reset and software reset.
9.1.1.
Hardware reset function
The S-7600A operates to be synchronous to the CLK signal(clock input). When the RESETX pin set to
low level in one clock period minimum, the S-7600A accept hardware reset input and starts initializing
internal circuit at positive edge timing of forth clock. After the RESETX pin return to high level, the S-
7600A maintains initialized state and turns normal state at positive edge timing of forth clock.
See the Figure 9-1.
RESETX
CLK
Min. 1 clock
1s 2n 3r ^4t 1s 2n 3r 4t
dh
d dh
initialized
normal
Figure 9-1
Hardware reset timing
9.1.2.
Software reset function
The S-7600A is able to initialize the internal circuit by the General Control Register(0x01). Show the
reset timing in case of x80 Family MPU mode. See the Figure 9-2.
CS
RS
WRITEX
SD7 to 0
BUSYX
CLK
Address
Data h01
Figure 9-2
normal state
80 Family MPU mode
initialized state
Software reset timing
normal state
Seiko Instruments Inc.
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