S-7600A Datasheet, PDF (5/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
LIST OF TABLES
TABLE 3.-1 PIN ASSIGNMENT ................................................................................................................................. 4
TABLE 3.-2 PIN DESCRIPTION ................................................................................................................................ 6
TABLE 4.-1 ABSOLUTE MAXIMUM RATINGS.................................................................................................. 8
TABLE 4.-2 RECOMMENDED OPERATING CONDITIONS ................................................................................. 8
TABLE 4.-3 DC CHARACTERISTICS ............................................................................................................. 9
TABLE 4.-4 POWER CURRENT CONSUMPTION ............................................................................................. 9
TABLE 5.-1 INTERFACE SELECTION ........................................................................................................... 10
TABLE 5.-2 CONNECTION RELATIONSHIP BETWEEN MPU AND PINS ........................................................... 10
TABLE 5.-3 68K FAMILY MPU WRITE CYCLE TIMING ................................................................................. 11
TABLE 5.-4 68K FAMILY MPU READ CYCLE TIMING.................................................................................. 12
TABLE 5.-5 X80 FAMILY MPU WRITE CYCLE TIMING ................................................................................ 13
TABLE 5.-6 X80 FAMILY MPU READ CYCLE TIMING.................................................................................. 14
TABLE 5.-7 SERIAL INTERFACE WRITE CYCLE TIMING .............................................................................. 15
TABLE 5.-8 SERIAL INTERFACE READ CYCLE TIMING ................................................................................ 16
TABLE 5.-9 INTERRUPT SELECTION TABLE ................................................................................................ 17
TABLE 6.-1 S-7600A MEMORY MAP (BANK 0).......................................................................................... 19
TABLE 6.-2 S-7600A MEMORY MAP (BANK 1).......................................................................................... 19
TABLE 7.-1 IAPI REGISTER MAP.............................................................................................................. 21
TABLE 7.-2 IAPI REGISTER MAP (CONTINUED)......................................................................................... 22
TABLE 7.-3 REVISION REGISTER BIT DEFINITIONS .................................................................................... 23
TABLE 7.-4 REVISION REGISTER DESCRIPTION ........................................................................................ 23
TABLE 7.-5 GENERAL CONTROL REGISTER BIT DEFINITIONS..................................................................... 23
TABLE 7.-6 GENERAL CONTROL REGISTER DESCRIPTION ......................................................................... 23
TABLE 7.-7 GENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ....................................................... 24
TABLE 7.-8 GENERIC SOCKET LOCATION REGISTER DESCRIPTION............................................................ 24
TABLE 7.-9 MASTER INTERRUPT REGISTER BIT DEFINITIONS .................................................................... 24
TABLE 7.-10 MASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED)................................................ 25
TABLE 7.-11 CONF STATUS REGISTER BIT DEFINITIONS ........................................................................... 25
TABLE 7.-12 CONF STATUS REGISTER DESCRIPTION ............................................................................... 26
TABLE 7.-13 SERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS............................................................ 27
TABLE 7.-14 SERIAL PORT INTERRUPT REGISTER DESCRIPTION ................................................................ 27
TABLE 7.-15 SERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS .................................................. 27
TABLE 7.-16 SERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION ...................................................... 27
TABLE 7.-17 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X10)............................................................ 28
TABLE 7.-18 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X11)............................................................ 28
TABLE 7.-19 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X12)............................................................ 29
TABLE 7.-20 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X13)............................................................ 29
TABLE 7.-21 INDEX REGISTER BIT DEFINITION .......................................................................................... 29
TABLE 7.-22 INDEX REGISTER DESCRIPTION ............................................................................................. 29
TABLE 7.-23 SOCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS.................................................... 30
TABLE 7.-24 SOCKET CONFIG STATUS LOW REGISTER DESCRIPTION ........................................................ 31
TABLE 7.-25 SOCKET STATUS MID REGISTER BIT DEFINITIONS.................................................................. 32
TABLE 7.-26 SOCKET STATUS MID REGISTER DESCRIPTION ...................................................................... 32
TABLE 7.-27 SOCKET ACTIVATE REGISTER BIT DEFINITIONS...................................................................... 33
TABLE 7.-28 SOCKET ACTIVATE REGISTER DESCRIPTION .......................................................................... 33
TABLE 7.-29 SOCKET INTERRUPT REGISTER BIT DEFINITIONS ................................................................... 33
TABLE 7.-30 SOCKET INTERRUPT REGISTER DESCRIPTION........................................................................ 34
TABLE 7.-31 SOCKET DATA AVAIL REGISTER BIT DEFINITIONS .................................................................. 34
TABLE 7.-32 SOCKET DATA AVAIL REGISTER DESCRIPTION....................................................................... 34
TABLE 7.-33 SOCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS.................................................. 35
TABLE 7.-34 SOCKET INTERRUPT MASK LOW REGISTER DESCRIPTION ...................................................... 35
TABLE 7.-35 SOCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS ................................................. 35
TABLE 7.-36 SOCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION...................................................... 35
TABLE 7.-37 SOCKET INTERRUPT LOW REGISTER BIT DEFINITIONS ........................................................... 36
TABLE 7.-38 SOCKET INTERRUPT LOW REGISTER DESCRIPTION ................................................................ 36
TABLE 7.-39 SOCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS........................................................... 36
Seiko Instruments Inc.
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