S-7600A Datasheet, PDF (20/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
5.2.2.2.
Read Cycle Timing
CS
RS
READX
WRITEX
TAW 8
SD7 to 0
BUSYX
CLK
TCC8
T_CYC8
TAW 8
TAH8
TCC8
TAH8
TAW 8
TCC8
TAH8
TDS8
Adress
TDH8
TACC8
Adress
TOH8
TACC8
Data
TOH8
TBD8
TBC8
TBOD8
Figure 5-7
x80 Family MPU Read Cycle Timing
Symbol Description
Min
Max
Notes
T_CYC8
T_AH8
T_AW8
T_DS8
T_DH8
T_ACC8
T_OH8
T_CC8
T_BD8
T_BC8
T_BOD8
System Cycle Time
Address Hold Time
Address Setup Time
Data Setup time
Data Hold Time
Access time
Output Disable Time
Control Pulse Width
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
100 ns
20ns
20ns
20ns
20 ns
-
20 ns
40 ns
-
2CLK
-
-
-
-
-
-
30ns
-
1.9CLK
30ns
-
30ns
CL=80pF
CL=80pF
CL=80pF
CL=80pF
NOTES:  CLK is the clock of S-7600A
 Timing is specified of 50% of the signal waveform.
 Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-6
x80 Family MPU Read Cycle Timing
14
Seiko Instruments Inc.