S-7600A Datasheet, PDF (21/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
5.3. Serial Interface
This mode is selected by pulling the PSX input pin “L”. In this mode Bit 6 of the Data Bus is used as the
serial clock and bit 5 and 7 are used as Data Input and Data Output. Bit 0 to 4 are high impedance. By
pulling WRITEX signal to “H” or “L”, the MPU performs a read or write operation.
5.3.1.
Write Cycle Timing
CS
RS
WRITEX
(R/WX)
SD6
(SCL)
SD7
(SI)
BUSYX
CLK
TASS
T_CYCS
TAHS
TASS
TAHS
TCLLS
TCLHS
TDSS
TDHS
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
TBDS
TBCS
TBODS
Figure 5-8
Serial Interface Write Timing
Symbol
Description
Min
Max
Notes
T_CYCS
T_CLLS
T_CLHS
T_ASS
T_AHS
T_DSS
T_DHS
T_BDS
T_BCS
T_BODS
System Cycle Time
Clock L Time
Clocl H Time
Address Setup Time
Address Hold Time
Data Setup time
Data Hold Time
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
100 ns
40ns
40 ns
20ns
20ns
20ns
20 ns
-
2CLK
-
1.9CLK
-
-
-
-
-
-
30ns
-
30ns
CL=80pF
CL=80pF
NOTES:  CLK is the clock of S-7600A
 Timing is specified of 50% of the signal waveform.
 Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-7
Serial Interface Write Cycle Timing
Seiko Instruments Inc.
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