S-7600A Datasheet, PDF (30/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
7.3.3.
Generic Socket Location Register (0x02)
(Read-Only)
This register is used to report back the location of general sockets to the software layer. Only bits [1:0]
will be set because the S-7600A chip is equipped with two general sockets.
Table 7-7
Generic Socket Location Register Bit Definitions
Bit
Def.
Value
7
6
5
4
3
2
1
0
S7
S6
S5
S4
S3
S2
S1
S0
0
0
0
0
0
0
1
1
Table 7-8
Bit
7
6
5
4
3
2
1
0
Generic Socket Location Register Description
Bit Name
S7
S6
S5
S4
S3
S2
S1
S0
Access
Description
R
Not available
R
Not available
R
Not available
R
Not available
R
Not available
R
Not available
R
General socket 1 available
R
General socket 0 available
7.3.4.
Master Interrupt (0x04)
(Read-Only, Default 0x00)
This direct register indicates the source of the S-7600A interrupt.
Table 7-9
Master Interrupt Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
-
-
-
-
-
PT_INT LINK_INT SOCK_INT
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.
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Seiko Instruments Inc.