S-7600A Datasheet, PDF (18/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
5.2.1.2.
CS
Read Cycle Timing
RS
WRITEX
(R/WX)
READX
(E)
SD7 to 0
TAW 6
TEW
TAW 6
TAH6
TCYC6
TEW
TAH6
TAW 6
TEW
TAH6
TDS6
Adress
TDH6
TACC6
Adress
TOH6
TACC6
Data
TOH6
BUSYX
CLK
TBD6
TBC6
TBOD6
Figure 5-5 68 Family MPU Read Timing
Symbol Description
Min
Max
Notes
T_CYC6
T_AH6
T_AW6
T_DS6
T_DH6
T_ACC6
T_OH6
T_EW
T_BD6
T_BC6
T_BOD6
System Cycle Time
Address Hold Time
Address Setup Time
Data Setup time
Data Hold Time
Access time
Output Disable Time
Enable Pulse Width
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
100 ns
20ns
20ns
20ns
20 ns
-
20 ns
40 ns
-
2CLK
-
-
-
-
-
-
30ns
-
1.9CLK
30ns
3CLK
30ns
CL=80pF
CL=80pF
CL=80pF
CL=80pF
NOTES:  CLK is the clock of S-7600A
 Timing is specified of 50% of the signal waveform.
 Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-4
68k Family MPU Read Cycle Timing
12
Seiko Instruments Inc.