S-7600A Datasheet, PDF (46/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
7.3.31. PPP Control and Status Register (0x60)
(Read/Write, Default 0x00)
This register control the PPP layer and reports its status.
Table 7-51
PPP Control and Status Register Bit Definitions (0x60)
Bit
7
6
Def. PPP_Int Con_Val
Default
0
0
5
Use_
PAP
0
4
3
2
1
0
TO_Dis PPP_Int_En Kick PPP_En PPP_Up
/SRst
0
0
0
0
0
Table 7-52
PPP Control Status Register Description
Bit
Bit Name
7
PPP_Int
6
Con_Val
5
Use_PAP
4
TO_Dis
3
PPP_Int_En
2
Kick
1
PPP_En
Access
R/W
R/W
R/W
R/W
R/W
W
R/W
Description
PPP Interrupt
This bit indicates that the PPP triggered an interrupt condition.
Read the PPP interrupt code register to determine the cause.
Writing a “1” to this bit position clears the interrupt.
Connection Valid
This bit indicates to the network stack that the underlying
connection is up and valid.
0 = Connection down
1 = Connection up
This bit enables PAP authentication within the PPP protocol. If
enabled, a PAP request is issued after PAP authentication is
negotiated. The PAP string enters through register 0x64.
0 = PAP disabled (default)
1 = PAP enabled
Timeouts Disabled
This bit disables the PPP block from timeouts for diagnostic
purposes. It should remain enable for normal operations.
0 = Timeouts enabled (default)
1 = Timeouts disabled
PPP Interrupt Enable
This bit enables the PPP interrupt.
0 = PPP Interrupt disabled (default)
1 = PPP Interrupt enabled
PPP Kick Start
When written to a 1, this bit will start the PPP if it falls into a
timeout condition. It clears once the kick operation performs.
This bit is self-clearing.
PPP Enable
This bit enables the PPP layer. The bit must be set before any
transmissions occur.
0 = PPP disabled (default)
1 = PPP enabled
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