S-7600A Datasheet, PDF (27/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
Table 7-1
iAPI Register Map
Add
Register
Bit Definitions
0x00
Revision
Major Revision Number
Minor Revision Number
0x01
General_Control
--
-
-
--
-
SW_
RST
0x02
General_Socket_
00
0
0 00
S1 S0
Location
0x04
Master_Interrupt
--
-
-
- ^{PT_ LINK} SOCK
INT _INT _{_INT}
0x08
Serial_Port_Config
S_ DCD
DA
V
DSR/ _{CTS RI DTR RTS SCTL}
HWFC
0x09
Serial_Port_Int
PT_ _-
INT
-
-
--
-
-
0x0A
Serial_Port_Int_
Mask
PINT DSINT_
-
-
--
-
-
_EN EN
0x0B
Serial_Port_Data
Serial Data Register
0x0C -
0x0D
BAUD_Rate_Div
BAUD Rate Divider Registers
0x10 - 0x13 Our_IP_Address
Our IP Address
0x1C
Clock_Div_Low
Low Byte for 1 kHz clock divider
0x1D
Clock_Div_High
High Byte for 1 kHz clock divider
0x20
Index
Socket index
0x21
TOS*
Type of Service Field
0x22
0x23
Socket_
Config_Status_Low*
Socket_Status_Mid*
TO
Buff_
Empty
URG
RST
Buff_
Full
Data_
Avail/
RST
- Protocol_Type
Term ConU
TCP State
0x24
Socekt_Activate
-
-
-
---
S1
S0
0x26
Socket_Interrupt
-
-
-
---
I1
I0
0x28
Socket_Data_Avail
-
-
-
-
-
- ^{DAV1 DAV0}
NOTE: 1)Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
2)Indexed registers are signified by an asterisk (*).
Seiko Instruments Inc.
21