S-7600A Datasheet, PDF (23/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
5.4. Interrupt
The interrupt signal outputs an active level while the interrupt flag is set in the interrupt register in the
S-7600A’s interrupt register. The interrupt signal returns to an inactive level if the flag clears. Show the
interrupt timing in the Figure 5-1.
The INT1 and INT2X can be Open Drain or CMOS output depending on the setting of INTCTL. The
INT1 and INT2X outputs are CMOS if INTCTL is “H” otherwise outputs are Open Drain. Table 5-9
defines the interrupt selection.
Interrupt flag
Set
Set
Reset
Reset
Table 5-9
INTCTL
INT1
H
H
L
H
H
L
L
Hi-Z
Interrupt Selection Table
INT2X
L
L
H
Hi-Z
CS
RS
WRITEX
SD7 to 0
BUSYX
CLK
INT1
Adress
Data
(x80 Family MPU mode, INTCTL=high)
Clear interrupt
Figure 5-1
INT1 interrupt timing
Seiko Instruments Inc.
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