S-7600A Datasheet, PDF (35/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
Table 7-19
Our IP Address Register Bit Definitions (0x12)
Bit
7
6
5
4
3
2
1
0
Def.
2nd byte of the local IP address
Default
0x00
Table 7-20
Our IP Address Register Bit Definitions (0x13)
Bit
7
6
5
4
3
2
1
0
Def.
Most significant byte of the local IP address
Default
0x00
7.3.11. Clock Divider Registers (0x1C-0x1D)
(Read/Write, Default 0x03E7)
These registers program the 1kHz clock generator. This clock is used internally for various S-7600A
timing functions. The following equation determines the value programmed into these registers:
(clk Freq/1 kHz) - 1 = Divide Count
Where clk Freq is S-7600A clock frequency. Therefore, for a 1 MHz clock, the divide count equals 1M /
1kHz - 1= 999 = 0x03e7.
7.3.12. Index Register (0x20)
(Read/Write, Default 0x00)
This register must be programmed prior to accessing indexed socket registers. Valid programmed
values are 0x00 and 0x01. If the socket number has not changed since the last access, this register
not need to be reprogrammed.
Table 7-21
Index Register Bit Definition
Bit
7
Def.
Default
6
5
4
3
2
1
0
Socket Index [7:0]
0x00
Table 7-22
Index Register Description
Bit
Bit Name
7:0
Socket_Index
Access
R/W
Description
0x00 : General Socket 0 Selected
0x01: General Socket 1 Selected
All other values are reserved
7.3.13. Type of Service Register (TOS) (0x21)
(Read/Write, Default 0x00)
This register configures the TOS field in the IP header for outgoing datagrams. It is an optional setting
that defaults to 0x00.
Seiko Instruments Inc.
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