S-7600A Datasheet, PDF (3/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
7.3.7. Serial Port Interrupt Mask Register (0x0A) ................................................................................. 27
7.3.8. Serial Port Data Register (0x0B) .................................................................................................. 28
7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................................ 28
7.3.10. Our IP Address Registers (0x10-0x13)...................................................................................... 28
7.3.11. Clock Divider Registers (0x1C-0x1D) ........................................................................................ 29
7.3.12. Index Register (0x20)................................................................................................................... 29
7.3.13. Type of Service Register (TOS) (0x21) ..................................................................................... 29
7.3.14. Socket Config Status Low Register (0x22) ............................................................................... 30
7.3.15. Socket Status Mid Register (0x23)............................................................................................. 32
7.3.16. Socket Activate Register (0x24) ................................................................................................. 33
7.3.17. Socket Interrupt Register (0x26)................................................................................................. 33
7.3.18. Socket Data Available Register (0x28) ...................................................................................... 34
7.3.19. Socket Interrupt Mask Low Register (0x2A) ............................................................................. 35
7.3.20. Socket Interrupt Mask High Register (0x2B) ............................................................................ 35
7.3.21. Socket Interrupt Low Register (0x2C)........................................................................................ 36
7.3.22. Socket Interrupt High Register (0x2D)....................................................................................... 36
7.3.23. Socket Data Register (0x2E) ...................................................................................................... 37
7.3.24. TCP Data Send and Buffer Out Length Registers (0x30 - 0x31)........................................... 37
7.3.25. Buffer In Length Registers (0x32-0x33) .................................................................................... 37
7.3.26. Urgent Pointer / UDP Datagram Size Registers (0x34-0x35) ................................................ 37
7.3.27. Their Port Registers (0x36-0x37) ............................................................................................... 38
7.3.28. Our Port Registers (0x38-0x39).................................................................................................. 38
7.3.29. Socket Status High Register (0x3A) .......................................................................................... 38
7.3.30. Their IP Address Registers (0x3C-0x3F) .................................................................................. 39
7.3.31. PPP Control and Status Register (0x60)................................................................................... 40
7.3.32. PPP Interrupt Code (0x61) .......................................................................................................... 41
7.3.33. PPP Max Retry, (0x62) ................................................................................................................. 41
7.3.34. PAP String (0x64) ......................................................................................................................... 42
8. SERIAL PORT INTERFACE ........................................................................................................................ 43
8.1. OVERVIEW ................................................................................................................................................. 43
8.2. SERIAL PORT REGISTER MAP................................................................................................................... 43
8.2.1. Hardware Flow Control (RTS/CTS Handshaking)....................................................................... 44
8.2.2. Serial Port Control............................................................................................................................ 44
9. RESET FUNCTIONS ..................................................................................................................................... 45
9.1. OVERVIEW ................................................................................................................................................. 45
9.1.1. Hardware reset function.................................................................................................................. 45
9.1.2. Software reset function ................................................................................................................... 45
10. APPLICATION EXAMPLES ....................................................................................................................... 46
10.1.1. In case of x80 Family MPU with LCD Controller ....................................................................... 46
10.1.2. In case of 68k Family MPU with LCD Controller ....................................................................... 47
10.1.3. In case of Serial interface with LCD Controller .......................................................................... 48
Seiko Instruments Inc.
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