S-7600A Datasheet, PDF (41/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
7.3.19. Socket Interrupt Mask Low Register (0x2A)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. Setting a bit enables the corresponding interrupt.
Table 7-33
Socket Interrupt Mask Low Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
TO_En ^Buff_
Buff_Full_En Data_Avail_En -
-
-
-
Emp_En
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-34
Socket Interrupt Mask Low Register Description
Bit
Bit Name
7 TO_En
6 Buff_Empty_En
5 Buff_Full_En
4 Data_Avail_En
Access
R/W
R/W
R/W
R/W
Description
Writing a “1” enables the Timeout interrupt.
Writing a “1” enables the Buffer Empty interrupt.
Writing a “1” enables the Buffer Full interrupt.
Writing a “1” enables the Data Available interrupt.
7.3.20. Socket Interrupt Mask High Register (0x2B)
(Read/Write, Default 0x00)
This register enables certain types of interrupt conditions. Setting bits enables their corresponding
interrupts.
Table 7-35
Socket Interrupt Mask High Register Bit Definitions
Bit
7
6
5
4
3
Def. URG_En RST_En Term_En ConU_En
-
2
1
0
-
-
-
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-36
Socket Interrupt Mask High Register Description
Bit
Bit Name
7 URG_En
6 RST_En
5 Term_En
4 ConU_En
Access
Description
R/W Writing a “1” to enable the Urgent Data interrupt.
R/W Writing a “1” to enable the Connection Reset interrupt.
R/W Writing a “1” to enable the Socket Termination
interrupt.
R/W Writing a “1” to enable the Connection Up interrupt.
Seiko Instruments Inc.
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