S-7600A Datasheet, PDF (12/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
3.3. Pin Description
The pins and signal descriptions are listed by function in Table 3-2.
Name
VDD1,VDD2
VSS1,VSS2
RESETX
TEST,
TI1 to TI7
TO1 to TO7
CLK
CTSX
DSRX
RI
RXD
DCD
DTRX
RTSX
TXD
RS
CS
C86
READX
PSX
WRITEX
INTCTRL
INT1
INT2X
BUSYX
SD7
SD6
SD5
SD0 to SD4
I/O
Description
- Positive power supply
- GND potential
I Reset input
I Test input (pull-down resistor is built in)
When normal use, connect to V_SS or open
O Test output
When normal use, connect to Vss or open
I Clock input
I Clear to send input
I Data set ready input
I Ring indicator input
I Serial received data input
I Data carrier detect input
O Data terminal ready output
O Request to send output
O Serial transmit data output
I Register selection input
I Chip selection input
I MPU interface mode selection input
68k mode : 1
x80 mode : 0
I x80 mode : read requirement input
68k mode : enable input
I parallel/serial interface selection input
I x80 mode : write requirement input
68k mode : read/write selection input
I INT1/INT2X drive type(CMOS/OD) selection input
*OT Interrupt output(active High) from S-7600A chip to MPU
*OT Interrupt output(active Low) from S-7600A chip to MPU
O busy indicator output
*B x80/68k mode : data bus
Serial mode : serial data input
*B x80/68k mode : data bus
Serial mode : serial clock input
*B x80/68k mode : data bus
Serial mode : serial data output
*B Data bus
*OT : Tri-state output
*B : bi-directional
Table 3-2
Pin Description
Type
A
B
D
C
C
C
C
C
C
D
D
D
C
C
C
C
C
C
C
E
E
D
F
F
F
F
6
Seiko Instruments Inc.