S-7600A Datasheet, PDF (29/55 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

S-7600A
Hardware Specification
7.3. Register Definitions
7.3.1.
Revision Register (0x00)
(Read-Only, Default 0x2110)
This direct read-only register reports back the design revision. See the design revision form in Table 7-
3 and Table 7-4.
Table 7-3
Revision Register Bit Definitions
Bit
Def.
Default
7
6
5
4
Major Revision Number
0x21
3
2
1
0
Minor Revision Number
0x10
Table 7-4
Revision Register Description
Bit
Bit Name
7:4
Major Revision
Number
3:0
Minor Revision
Number
Access
R
R
Description
This nibble indicates the major revision number for
the S-7600A core.
This nibble indicates the minor revision number for
the S-7600A core.
7.3.2.
General Control Register (0x01)
(Read/Write, Default 0x00)
This direct register contains the master software reset. See the register format in Table 7-5 and Table
7-6.See the wave format in figure 9.-2.
Table 7-5
General Control Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
-
-
-
-
-
-
-
SW_RST
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-6
General Control Register Description
Bit
Bit Name
0
SW_RST
Access
R/W
Description
Software Reset.
This active high reset returns the S-7600A core to
power-on reset settings. It is self-clearing and
does not need to be written to “0” for proper
operations.
0 = Normal operation
1 = Soft reset
Seiko Instruments Inc.
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