AM186 Datasheet, PDF (93/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (33 MHz)
Preliminary
Parameter
33 MHz
No. Symbol Description
Min
Max Unit
CLKIN Requirements for Times Four Mode
36
t_CKIN
X1 Period^(a)
120
125
ns
37
t_CLCK X1 Low Time (1.5 V)^(a)
55
ns
38
t_CHCK X1 High Time (1.5 V)^(a)
55
ns
39
t_CKHL X1 Fall Time (3.5 to 1.0 V)^(a)
5
ns
40
t_CKLH X1 Rise Time (1.0 to 3.5 V)^(a)
5
ns
CLKIN Requirements for Times One Mode
36
t_CKIN
X1 Period^(a)
30
60
ns
37
t_CLCK X1 Low Time (1.5 V)^(a)
10
ns
38
t_CHCK X1 High Time (1.5 V)^(a)
39
t_CKHL X1 Fall Time (3.5 to 1.0 V)^(a)
40
t_CKLH X1 Rise Time (1.0 to 3.5 V)^(a)
CLKIN Requirements for Divide by Two Mode
36
t_CKIN
X1 Period^(a)
T ³⁷
t_{CLCK X1 Low Time (1.5 V)}^(a)
38
t_{CHCK X1 High Time (1.5 V)}^(a)
39
t_{CKHL X1 Fall Time (3.5 to 1.0 V)}^(a)
F ⁴⁰
t_{CKLH X1 Rise Time (1.0 to 3.5 V)}^(a)
CLKOUT Timing
10
ns
5
ns
5
ns
15
33
ns
2.5
ns
2.5
ns
5
ns
5
ns
42
t_CLCL CLKOUTA Period
43
t_CLCH CLKOUTA Low Time (C_L=50 pF)
44
t_CHCL CLKOUTA High Time (C_L=50 pF)
A ₄₅
t_CH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V)
46
t_CL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V)
61
t_LOCK Maximum PLL Lock Time
69
t_CICOA X1 to CLKOUTA Skew
R ₇₀
t_CICOB X1 to CLKOUTB Skew
30
ns
0.5t_CLCL – 1.5 = 13.5
ns
0.5t_CLCL – 1.5 = 13.5
ns
3
ns
3
ns
1
ms
20
ns
26
ns
Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
D ^{output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.}
a The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
93