AM186 Datasheet, PDF (87/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
Interrupt Acknowledge Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
25 MHz
33 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Requirements
1
t_DVCL Data in Setup
10
8
ns
2
t_CLDX Data in Hold
3
3
ns
General Timing Responses
3
t_{CHSV Status Active Delay}
0
20
0
15 ns
4
t_{CLSH Status Inactive Delay}
0
20
0
15 ns
7
t_{CLDV Data Valid Delay}
0
20
0
15 ns
8
t_{CHDX Status Hold Time}
0
0
ns
9
t_{CHLH ALE Active Delay}
20
15 ns
10
t_{LHLL ALE Width}
t_CLCL – 10 = 30
t_CLCL – 10 = 20
ns
11
t_{CHLL ALE Inactive Delay}
20
15 ns
12
t_{AVLL AD Address Invalid to ALE Low}^(a)
t_CLCH
t_CLCH
ns
15
t_{CLAZ AD Address Float Delay}
t_CLAX = 0
20
t_CLAX =0
15 ns
19
t_{DXDL DEN Inactive to DT/R Low}^(a)
0
0
ns
T ₂₀
t_{CVCTV Control Active Delay 1}^(b)
0
20
0
15 ns
21 ^t_CVDEX DEN Inactive Delay
0
20
0
15 ns
22
t_{CHCTV Control Active Delay 2}^(c)
0
20
0
15 ns
F ²³
t_{LHAV ALE High to Address Valid}
15
10
ns
31
t_{CVCTX Control Inactive Delay}^(b)
0
20
0
15 ns
68
t_{CHAV CLKOUTA High to A Address Valid}
0
20
0
15 ns
Notes:
A ^{All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All}
output test conditions are with C_L=50 pF. For switching tests, V_IL=0.3 V and V_IH =V_CC–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the INTA1–INTA0 signals.
D ^{R c This parameter applies to the DEN and DT/R signals.}
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
87