AM186 Datasheet, PDF (41/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

BUS OPERATION
BUS INTERFACE UNIT
The industry-standard 80C186/80C188 microcontrol- The bus interface unit controls all accesses to external
lers use a multiplexed address and data (AD) bus. The peripherals and memory devices. External accesses
address is present on the AD bus only during the t₁
clock phase. The Am186ER and Am188ER microcon-
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
trollers continue to provide the multiplexed AD bus and, peripheral control block. The Am186ER and Am188ER
in addition, provide a nonmultiplexed address (A) bus. microcontrollers provide an enhanced bus interface
The A bus provides an address to the system for the unit with the following features:
complete bus cycle (t₁–t₄).
n A nonmultiplexed address bus
For systems where power consumption is a concern,
the address can be disabled from being driven on the
AD bus on the Am186ER microcontroller and on the
AD and AO buses on the Am188ER microcontroller
during the normal address portion of the bus cycle for
n Separate byte write enables for high and low bytes
on the Am186ER microcontroller and a write enable
on the Am188ER microcontroller
n Pseudo Static RAM (PSRAM) support
accesses to UCS and/or LCS address spaces. In this The standard 80C186/80C188 multiplexed address
mode, the affected bus is placed in a high-impedance and data bus requires system interface logic and an ex-
state during the address portion of the bus cycle. This ternal address latch. On the Am186ER and Am188ER
feature is enabled through the DA bits in the UMCS and
LMCS registers. When address disable is in effect, the
number of signals that assert on the bus during all nor-
mal bus cycles to the associated address space is re-
duced, thus decreasing power consumption, reducing
processor switching noise, and preventing bus conten-
T ^{tion with memory devices and peripherals when oper-}
ating at high clock rates. On the Am188ER
microcontroller, the address is driven on A015–A08
during the data portion of the bus cycle, regardless of
F ^{the setting of the DA bits.}
If the ADEN pin is pulled Low during processor reset,
the value of the DA bits in the UMCS and LMCS regis-
ters is ignored and the address is driven on the AD bus
for all accesses, thus preserving the industry-standard
A _{80C186 and 80C188 microcontrollers’ multiplexed ad-}
dress bus and providing support for existing emulation
tools.
Figure 4 on page 42 shows the affected signals during
R ^{a normal read or write operation for an Am186ER mi-}
crocontroller. The address and data will be multiplexed
onto the AD bus.
Figure 5 on page 42 shows an Am186ER microcontrol-
ler bus cycle when address bus disable is in effect. This
D _{results in having the AD bus operate in a nonmulti-}
plexed data-only mode. The A bus will have the ad-
dress during a read or write operation.
microcontrollers, new byte write enables, PSRAM con-
trol logic, and a new nonmultiplexed address bus can
reduce design costs by eliminating this external logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid one-
half CLKOUTA cycle in advance of the address on the
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte write enable sig-
nals, the A19–A0 bus provides a seamless interface to
external SRAM, PSRAM, and Flash/EPROM memory
systems.
Byte Write Enables
The Am186ER microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals
which act as byte write enables. The Am188ER micro-
controller provides the WB (Write Byte) signal which
acts as a write enable.
WHB is the logical AND of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
AND of A0 and WR. WLB is Low when A0 and WR are
both Low. WB is Low whenever a byte is written by the
Am188ER microcontroller.
The byte write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
Figure 6 on page 43 shows the affected signals during a
Output Enable
normal read or write operation for an Am188ER micro- The Am186ER and Am188ER microcontrollers provide
controller. The multiplexed address/data mode is com- the RD (Read) signal which acts as an output enable.
patible with the 80C188 microcontrollers and might be
used to take advantage of existing logic or peripherals.
The RD signal is Low when a word or byte is read by
the Am186ER or Am188ER microcontroller.
Figure 7 on page 43 shows an Am188ER microcontrol-
ler bus cycle when address bus disable is in effect. The
address and data is not multiplexed. The AD7–AD0
signals will have only data on the bus, while the A bus
will have the address during a read or write operation.
The AO bus will also have the address during t₂–t₄.
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
41