AM186 Datasheet, PDF (81/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
25 MHz
33 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Responses
5 t_CLAV AD Address Valid Delay
0
20
0
15 ns
7 t_CLDV Data Valid Delay
0
20
0
15 ns
8 t_CHDX Status Hold Time
0
0
ns
9 t_CHLH ALE Active Delay
20
15 ns
10 t_LHLL ALE Width
t_CLCL – 10 = 30
t_CLCL – 10 = 20
ns
11 t_CHLL ALE Inactive Delay
20
15 ns
23 t_LHAV ALE High to Address Valid
15
0
15 ns
20 t_CVCTV Control Active Delay 1^(b)
0
20
10
ns
80 t_CLCLX LCS Inactive Delay
81 t_CLCSL LCS Active Delay
84 t_LRLL LCS Precharge Pulse Width
Write Cycle Timing Responses
30 t_CLDOX Data Hold Time
T 31 t_CVCTX Control Inactive Delay^(b)
32 t_WLWH WR Pulse Width
33 t_WHLH WR Inactive to ALE High^(a)
F ^{34 tWHDX Data Hold after WR(a)}
65 t_AVWL A Address Valid to WR Low
68
t_CHAV
CLKOUTA High to A
Address Valid
A ⁸⁷
t_AVBL
A Address Valid to WHB, WLB
Low
0
0
t_CLCL + t_CLCH –3
0
0
2t_CLCL – 10 = 70
t_CLCH – 2
t_CLCL – 10 = 30
t_CLCL + t_CHCL – 3
0
t_CHCL – 3
20
0
15 ns
20
0
15 ns
t_CLCL + t_CLCH –3
0
ns
20
0
15 ns
2t_CLCL – 10 = 50
ns
t_CLCH – 2
ns
t_CLCL – 10 = 20
ns
t_CLCL + t_CHCL – 3
ns
20
0
15 ns
20
t_CHCL – 3
15 ns
Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C_L=50 pF. For switching tests, V_IL=0.3 V and V_IH =V_CC–0.3 V.
a Testing is performed with equal loading on referenced pins.
D ^{R b This parameter applies to the DEN, WR, WHB and WLB signals.}
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
81