AM186 Datasheet, PDF (68/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Alphabetical Key to Switching Parameter Symbols
Parameter
Symbol No. Description
Parameter
Symbol No. Description
t_ARYCH
t_ARYCHL
t_ARYLCL
t_AVBL
t_AVCH
t_AVLL
t_AVRL
t_AVWL
t_AZRL
t_CH1CH2
t_CHAV
t_CHCK
t_CHCL
t_CHCSV
t_CHCSX
t_CHCTV
t_CHCV
t_CHCZ
t_CHDX
t_CHLH
t_CHLL
t_CHRFD
t_CHSV
t_CICOA
t_CICOB
t_CKHL
t_CKIN
t_CKLH
t_CL2CL1
t_CLARX
t_CLAV
t_CLAX
t_CLAZ
t_CLCH
t_CLCK
t_CLCL
t_CLCLX
t_CLCSL
t_CLCSV
t_CLDOX
49 ARDY Resolution Transition Setup Time
t_CLDX
2
51 ARDY Inactive Holding Time
t_CLEV
71
52 ARDY Setup Time
t_CLHAV
62
87 A Address Valid to WHB, WLB Low
t_CLRF
82
14 AD Address Valid to Clock High
t_CLRH
27
12 AD Address Valid to ALE Low
t_CLRL
25
66 A Address Valid to RD Low
t_CLSH
4
65 A Address Valid to WR Low
t_CLSL
72
24 AD Address Float to RD Active
t_CLSRY
48
45 CLKOUTA Rise Time
t_CLTMV
55
68 CLKOUTA High to A Address Valid
t_COAOB
83
38 X1 High Time
t_CVCTV
20
44 CLKOUTA High Time
t_CVCTX
31
67 CLKOUTA High to LCS/UCS Valid
t_CVDEX
21
18 MCS/PCS Inactive Delay
t_CXCSX
17
22 Control Active Delay 2
t_DVCL
1
64 Command Lines Valid Delay (after Float)
t_DVSH
75
63 Command Lines Float Delay
t_DXDL
19
8 Status Hold Time
9 ALE Active Delay
11 ALE Inactive Delay
79 CLKOUTA High to RFSH Valid
3 Status Active Delay
69 X1 to CLKOUTA Skew
70 X1 to CLKOUTB Skew
39 X1 Fall Time
36 X1 Period
40 X1 Rise Time
R _{46 CLKOUTA Fall Time}
50 ARDY Active Hold Time
5 AD Address Valid Delay
D^{6 Address Hold}
A^tHVCL
58
t_INVCH
53
t_INVCL
54
t_LCRF
86
t_LHAV
23
t_LHLL
10
t_LLAX
13
t_LOCK
61
t_LRLL
84
t_RESIN
57
t_RFCY
85
t_RHAV
29
t_RHDX
59
t_RHLH
28
15 AD Address Float Delay
t_RLRH
26
43 CLKOUTA Low Time
t_SHDX
77
37 X1 Low Time
t_SLDV
78
42 CLKOUTA Period
t_SRYCL
47
80 LCS Inactive Delay
t_WHDEX
35
81 LCS Active Delay
t_WHDX
34
16 MCS/PCS Active Delay
t_WHLH
33
30 Data Hold Time
t_WLWH
32
Data in Hold
CLKOUTA Low to SDEN Valid
HLDA Valid Delay
CLKOUTA High to RFSH Invalid
RD Inactive Delay
RD Active Delay
Status Inactive Delay
CLKOUTA Low to SCLK Low
SRDY Transition Hold Time
Timer Output Delay
CLKOUTA to CLKOUTB Skew
F ^{T Control Active Delay 1}
Control Inactive Delay
DEN Inactive Delay
MCS/PCS Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
DEN Inactive to DT/R Low
HOLD Setup
Peripheral Setup Time
DRQ Setup Time
LCS Inactive to RFSH Active Delay
ALE High to Address Valid
ALE Width
AD Address Hold from ALE Inactive
Maximum PLL Lock Time
LCS Precharge Pulse Width
RES Setup Time
RFSH Cycle Time
RD Inactive to AD Address Active
RD High to Data Hold on AD Bus
RD Inactive to ALE High
RD Pulse Width
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
SRDY Transition Setup Time
WR Inactive to DEN Inactive
Data Hold after WR
WR Inactive to ALE High
WR Pulse Width
t_CLDV
7 Data Valid Delay
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
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Am186^TMER and Am188^TMER Microcontrollers Data Sheet