AM186 Datasheet, PDF (71/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
50 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Requirements
1
t_DVCL Data in Setup
2
t_CLDX Data in Hold^(c)
General Timing Responses
5
5
ns
2
2
ns
3
t_CHSV Status Active Delay
4
t_CLSH Status Inactive Delay
5
t_CLAV AD Address Valid Delay
7
t_CLDV Data Valid Delay
8
t_CHDX Status Hold Time
9
t_CHLH ALE Active Delay
10
t_LHLL ALE Width
11
t_CHLL ALE Inactive Delay
12
t_AVLL AD Address Valid to ALE Low^(a)
13
t_LLAX
AD Address Hold from ALE
Inactive^(a)
14
t_AVCH AD Address Valid to Clock High
15
t_CLAZ AD Address Float Delay
16
t_CLCSV MCS/PCS Active Delay
17
t_CXCSX
MCS/PCS Hold from Command
Inactive^(a)
18
t_CHCSX MCS/PCS Inactive Delay
19
t_DXDL DEN Inactive to DT/R Low^(a)
20
t_CVCTV Control Active Delay 1^(b)
21
t_CVDEX DEN Inactive Delay
22
t_CHCTV Control Active Delay 2^(b)
23
t_LHAV ALE High to Address Valid
Read Cycle Timing Responses
R ²⁴
t_AZRL AD Address Float to RD Active
25
t_CLRL RD Active Delay
26
t_RLRH RD Pulse Width
D²⁷
t_CLRH RD Inactive Delay
28
t_RHLH RD Inactive to ALE High^(a)
0
12
0
12
0
12
0
12
0
12
t_CLCL – 5 = 20
12
t_CLCH
t_CHCL
0
t_CLAX = 0
12
A⁰
12
t_CLCH
0
12
0
0
12
0
14
0
12
7.5
0
0
10
2t_CLCL–10=40
0
12
t_CLCH – 2
0
0
0
0
0
15
t_CLCH
FtCHCL
0
0
0
t_CLCH
0
0
0
0
0
5
10 ns
10 ns
10 ns
10 ns
ns
10 ns
T^ns
10 ns
ns
ns
ns
10 ns
10 ns
ns
10 ns
ns
10 ns
14 ns
10 ns
ns
0
0
35
0
t_CLCH – 2
ns
10 ns
ns
10 ns
ns
29
t_RHAV
RD Inactive to AD Address
Active^(a)
t_CLCL – 5 = 20
15
ns
59
t_RHDX RD High to Data Hold on AD Bus^(c)
0
0
ns
66
t_AVRL A Address Valid to RD Low
2 • t_CLCL–10=40
2 • t_CLCL–10=30
ns
67
t_CHCSV CLKOUTA High to LCS/UCS Valid
0
12
0
10 ns
68
t_CHAV CLKOUTA High to A Address Valid
0
10
0
10 ns
Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C_L=50 pF. For switching tests, V_IL=0.3 V and V_IH =V_CC–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
71