AM186 Datasheet, PDF (70/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
25 MHz
33 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Requirements
1
t_DVCL Data in Setup
2
t_CLDX Data in Hold^(c)
General Timing Responses
10
8
ns
3
3
ns
3
t_CHSV Status Active Delay
4
t_CLSH Status Inactive Delay
5
t_CLAV AD Address Valid Delay
7
t_CLDV Data Valid Delay
8
t_CHDX Status Hold Time
9
t_CHLH ALE Active Delay
10
t_LHLL ALE Width
11
t_CHLL ALE Inactive Delay
12
t_AVLL AD Address Valid to ALE Low^(a)
13
t_LLAX AD Address Hold from ALE Inactive^(a)
14
t_AVCH AD Address Valid to Clock High
15
t_CLAZ AD Address Float Delay
16 t_CLCSV MCS/PCS Active Delay
17
t_CXCSX
MCS/PCS Hold from Command
Inactive^(a)
18 t_CHCSX MCS/PCS Inactive Delay
19
t_DXDL DEN Inactive to DT/R Low^(a)
20
t_CVCTV Control Active Delay 1^(b)
21 t_CVDEX DEN Inactive Delay
22
t_CHCTV Control Active Delay 2^(b)
23
t_LHAV ALE High to Address Valid
Read Cycle Timing Responses
24
t_AZRL AD Address Float to RD Active
R ₂₅
t_CLRL RD Active Delay
26
t_RLRH RD Pulse Width
27
t_CLRH RD Inactive Delay
D ²⁸
t_RHLH RD Inactive to ALE High^(a)
29
t_RHAV RD Inactive to AD Address Active^(a)
59
t_RHDX RD High to Data Hold on AD Bus^(c)
66
t_AVRL A Address Valid to RD Low
67 t_CHCSV CLKOUTA High to LCS/UCS Valid
68
t_CHAV CLKOUTA High to A Address Valid
0
20
0
20
0
20
0
20
0
20
t_CLCL – 10 = 30
20
t_CLCH
t_CHCL
0
t_CLAX = 0
20
0
20
A^tCLCH
0
20
0
0
20
0
20
0
20
15
0
0
20
2t_CLCL – 15 = 65
0
20
t_CLCH – 3
t_CLCL – 10 = 30
0
2t_CLCL – 15 = 65
0
20
0
20
0
0
0
0
0
t_CLCL – 10 = 20
t_CLCH
FtCHCL
0
t_CLAX = 0
0
t_CLCH
0
0
0
0
0
10
0
0
2t_CLCL – 15 = 45
0
t_CLCH – 3
t_CLCL – 10 = 20
0
2t_CLCL – 15 = 45
0
0
15 ns
15 ns
15 ns
15 ns
ns
15 ns
Tns
15 ns
ns
ns
ns
15 ns
15 ns
ns
15 ns
ns
15 ns
15 ns
15 ns
ns
ns
15 ns
ns
15 ns
ns
ns
ns
ns
15 ns
15 ns
Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C_L=50 pF. For switching tests, V_IL=0.3 V and V_IH =V_CC–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
70
Am186^TMER and Am188^TMER Microcontrollers Data Sheet