AM186 Datasheet, PDF (49/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

CHIP-SELECT UNIT
control register (UMCS, LMCS, MMCS, PACS, and
The Am186ER and Am188ER microcontrollers contain
logic that provides programmable chip-select genera-
tion for both memories and peripherals. The logic can
be programmed to provide external ready and wait-
MPCS) contains a single-bit field that determines
whether the external ready signal is required or ig-
nored. The internal memory ignores the external ready
signal.
state generation and latched address bits A1 and A2. The number of wait states to be inserted for each ac-
The chip-select lines are active for all memory and I/O cess to an external peripheral or memory region is pro-
cycles in their programmed areas, whether they are grammable. The chip-select control registers for UCS,
generated by the CPU or by the integrated DMA unit.
LCS, MCS3–MCS0, PCS6, and PCS5 contain a two-bit
Chip-Select Timing
field that determines the number of wait states from
zero to three to be inserted. PCS3–PCS0 use three bits
The timing for the UCS and LCS outputs is modified to provide additional values of 5, 7, 9, and 15 wait
from the original Am186 microcontroller. These outputs states. The chip-select control register for internal
now assert in conjunction with the nonmultiplexed ad- memory always specifies no wait states.
dress bus for normal memory timing. To enable these
outputs to be available earlier in the bus cycle, the num-
ber of programmable memory size selections has been
reduced.
Ready and Wait-State Programming
The Am186ER and Am188ER microcontrollers can be
programmed to sense a ready signal for each of the ex-
ternal peripheral or memory chip-select lines. The ex-
ternal ready signal can be either the ARDY or SRDY
T _{signal as shown in Figure 11. For diagrams of the syn-}
chronous ready waveforms and asynchronous ready
waveforms, refer to page 97. Each external chip-select
When external ready is required, internally pro-
grammed wait states will always complete before exter-
nal ready can terminate or extend a bus cycle. For
example, if the internal wait states are set to insert two
wait states, the processor samples the external ready
pin during the first wait cycle. If external ready is as-
serted at that time, the access completes after six cy-
cles (four cycles plus two wait states). If external ready
is not asserted during the first wait state, the access is
extended until ready is asserted, which is followed by
one more wait state followed by t₄.
F _ARDY
A _CLKOUTA
D
Q
Rising Edge
Bus Ready
R_D
Q
D ^{Falling Edge}
SRDY
D
Q
Falling Edge
Figure 11. ARDY and SRDY Synchronization Logic Diagram
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
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