AM186 Datasheet, PDF (78/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
25 MHz
33 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Requirements
1
t_DVCL Data in Setup
10
8
ns
2
t_CLDX Data in Hold^(b)
3
3
ns
General Timing Responses
5
t_CLAV AD Address Valid Delay
0
20
0
15 ns
7
t_CLDV Data Valid Delay
0
20
0
15 ns
8
t_CHDX Status Hold Time
0
0
ns
9
t_CHLH ALE Active Delay
20
15 ns
10
t_LHLL ALE Width
t_CLCL – 10 = 30
t_CLCL – 10 = 20
ns
11
t_CHLL ALE Inactive Delay
20
15 ns
23
t_LHAV ALE High to Address Valid
15
10
ns
80 t_CLCLX LCS Inactive Delay
0
20
0
15 ns
81 t_CLCSL LCS Active Delay
0
20
0
15 ns
84
t_LRLL LCS Precharge Pulse Width
t_CLCL + t_CLCH –3
t_CLCL + t_CLCH –3
ns
T Read Cycle Timing Responses
24
t_{AZRL AD Address Float to RD Active}
0
0
ns
25
t_{CLRL RD Active Delay}
0
20
0
15 ns
F ²⁶
t_{RLRH RD Pulse Width}
2t_CLCL – 15 = 65
2t_CLCL – 15 = 45
ns
27
t_{CLRH RD Inactive Delay}
28
t_{RHLH RD Inactive to ALE High}^(a)
0
20
0
15 ns
t_CLCH – 3
t_CLCH – 3
ns
59
t_{RHDX RD High to Data Hold on AD Bus}^(b)
0
0
ns
A ⁶⁶
t_{AVRL A Address Valid to RD Low}
2t_CLCL – 15 = 65
2t_CLCL – 15 = 45
ns
68
t_{CHAV CLKOUTA High to A Address Valid}
0
20
0
15 ns
Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C_L=50 pF. For switching tests, V_IL=0.3 V and V_IH =V_CC–0.3 V.
R _{a Testing is performed with equal loading on referenced pins.}
D ^{b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.}
78
Am186^TMER and Am188^TMER Microcontrollers Data Sheet