AM186 Datasheet, PDF (10/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

REVISION HISTORY
Date
Rev Description
Feb. 2000
D
Replaced block diagrams on page 2 and page 3 with updated diagrams showing that the internal data
bus interfaces via the BIU and not RAM.
Feb. 2000 D Added new industrial parts for “Ordering Information” on page 4.
Feb. 2000 D Updated product listings and customer service matter on page 12 and page 13.
Feb. 2000 D Replaced Figure 8 on page 45 (microcontroller oscillator configurations) with updated figure.
Feb. 2000
D
Updated several references to watchdog timer on page 54 to reflect that the WDT is inactive after
reset, not active).
Feb. 2000
D
Provided a value for the TBD in the table entitled, “DC Characteristics Over Commercial and Industrial
Operating Ranges” on page 60.
Feb. 2000
Feb. 2000
Feb. 2000
T ^{Feb. 2000}
Feb. 2000
F _{Feb. 2000}
Feb. 2000
A ^{Feb. 2000}
Feb. 2000
Feb. 2000
R _{Feb. 2000}
D^{Feb. 2000}
D
Updated table title and "Min" values for No. 66 in the switching characteristics table, “Read Cycle (40
MHz and 50 MHz)” on page 71.
D
Updated table title and "Max" values for No. 87 in the switching characteristics table, “Write Cycle (40
MHz and 50 MHz)” on page 74.
D
Updated table title and "Min" value for No. 9 (50 MHz) in the switching characteristics table, “Internal
RAM Show Read Cycle (40 MHz and 50 MHz)” on page 76.
D
Updated table title and "Min" values for No. 66 in the switching characteristics table, “PSRAM Read
Cycle (40 MHz and 50 MHz)” on page 79.
D
Updated table title and "Max" value for No. 68 (40 MHz) in the switching characteristics table,
“PSRAM Write Cycle (40 MHz and 50 MHz)” on page 82.
D
Updated table title in the switching characteristics table, “PSRAM Refresh Cycle (40 MHz and 50
MHz)” on page 85.
D
Updated table title in the switching characteristics table, “Software Halt Cycle (40 MHz and 50 MHz)”
on page 90.
D Updated "Min" and "Max" values in the switching characteristics table, “Clock (33 MHz)” on page 93.
D Updated table title in the switching characteristics table, “Clock (40 MHz and 50 MHz)” on page 94.
D
Updated table title in the switching characteristics table, “Ready and Peripheral Timing (40 MHz and
50 MHz)” on page 96.
D
Updated table title in the switching characteristics table, “Reset and Bus Hold (40 MHz and 50 MHz)”
on page 99.
D
Updated table title in the switching characteristics table, “Synchronous Serial Interface (SSI) (40 MHz
and 50 MHz)” on page 102.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle
(40 MHz and 50 MHz)", row 9, column "50 MHz" - "Min", the "0" is deleted.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle
(40 MHz and 50 MHz)", row 66, column "40 MHz" - "Min", the value is changed.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle
(40 MHz and 50 MHz)", row 66, column "50 MHz" - "Min", the value is changed.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges PSRAM
Write Cycle (40 MHz and 50 MHz)", row 68, column "40 MHz" - "Max", the value is changed.
May 2000
D
Under “Key Features and Benefits” on page 14, in the third bullet "Enhanced functionality," the
feature, "a PSRAM controller" was added.
May 2000
D
Under “HOLD” on page 32, the sentence, "A HOLD request is second only to DRAM or PSRAM
refresh requests in priority of activity requests received by the processor." is changed.
10
Am186^TMER and Am188^TMER Microcontrollers Data Sheet