AM186 Datasheet, PDF (55/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

DMA Operation
For DMA from the asynchronous serial port, the re-
Each channel has six registers in the peripheral control
block that define specific channel operations. The DMA
registers consist of a 20-bit source address (two regis-
ters), a 20-bit destination address (two registers), a 16-
bit transfer count register, and a 16-bit control register.
ceive data register address, either I/O-mapped or
memory-mapped, should be specified as a byte source
for the DMA by writing the address of the register into
the DMA Source and DMA Source High registers. The
source address (the address of the receive data regis-
ter) should be configured as a constant throughout the
The DMA transfer count register (DTC) specifies the DMA. The asynchronous serial port receiver acts as
number of DMA transfers to be performed. Up to 64K the synchronizing device; therefore, the DMA channel
transfers can be performed with automatic termination. should be configured as source- synchronized.
The DMA control registers define the channel opera-
tion. All registers can be modified during any DMA ac-
DMA Channel Control Registers
tivity. Any changes made to the DMA registers are Each DMA control register determines the mode of op-
reflected immediately in DMA operation.
eration for the particular DMA channel. This register
The Am188ER microcontroller’s maximum DMA trans-
specifies the following:
fer rates are half that of those listed in Table 9 for the n Mode of synchronization
Am186ER microcontroller.
n Whether bytes or words are transferred (Am186ER
Table 9. Am186ER Microcontroller Maximum DMA
Transfer Rates
Synchronization Type
T _{Unsynchronized}
Source Synch
F _{Destination Synch}
(CPU needs bus)
Destination Synch
(CPU does not need bus)
Maximum DMA
Transfer Rate (Mbyte/s)
50 40 33 25
MHz MHz MHz MHz
12.5 10 8.25 6.25
12.5 10 8.25 6.25
8.33 6.6 5.5 4.16
10.00 8 6.6 5
A _{Asynchronous Serial Port/DMA Transfers}
The enhanced Am186ER/Am188ER microcontrollers
can DMA to and from the asynchronous serial port.
This is accomplished by programming the DMA con-
R _{troller to perform transfers between a data buffer (lo-}
cated either in memory or I/O space) and an
asynchronous serial port data register (SPTD or
SPRD). Note that when a DMA channel is in use by the
D ^{asynchronous serial port, the corresponding external}
microcontroller only)
n Whether an interrupt is generated after the last
transfer
n Whether DMA activity ceases after a programmed
number of DMA cycles
n Relative priority of the DMA channel with respect to
the other DMA channel
n Whether the source address is incremented, decre-
mented, or maintained constant after each transfer
n Whether the source address addresses memory or
I/O space
n Whether the destination address is incremented,
decremented, or maintained constant after trans-
fers
n Whether the destination address addresses mem-
ory or I/O space
DMA Priority
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles, except between
locked memory accesses or word accesses to odd
DMA request signal is deactivated.
memory locations. However, an external bus hold takes
For DMA to the asynchronous serial port, the transmit
priority over an internal DMA cycle.
data register address, either I/O-mapped or memory-
mapped, should be specified as a byte destination for
the DMA by writing the address of the register into the
DMA destination low and DMA destination high regis-
ters. The destination address (the address of the trans-
mit data register) should be configured as a constant
throughout the DMA operation. The asynchronous se-
rial port transmitter acts as the synchronizing device;
Because an interrupt request, other than an NMI, can-
not suspend a DMA operation and the CPU cannot ac-
cess memory during a DMA cycle, interrupt latency
time suffers during sequences of continuous DMA cy-
cles. An NMI request, however, causes all internal
DMA activity to halt. This allows the CPU to respond
quickly to the NMI request.
therefore, the DMA channel should be configured as
destination-synchronized.
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
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