AM186 Datasheet, PDF (82/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
50 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Responses
5
t_CLAV AD Address Valid Delay
0
12
0
10
ns
7
t_CLDV Data Valid Delay
0
12
0
10
ns
8
t_CHDX Status Hold Time
0
0
ns
9
t_CHLH ALE Active Delay
12
10
ns
10
t_LHLL ALE Width
t_CLCL – 5 = 20
15
ns
11
t_CHLL ALE Inactive Delay
20
t_CVCTV Control Active Delay 1^(b)
12
10
ns
0
12
0
10
ns
23
t_LHAV ALE High to Address Valid
7.5
5
ns
80
t_CLCLX LCS Inactive Delay
0
12
0
10
ns
81
t_CLCSL LCS Active Delay
0
12
0
10
ns
84
t_LRLL LCS Precharge Pulse Width
t_CLCL + t_CLCH –1.25
t_CLCL + t_CLCH –1
Write Cycle Timing Responses
30
t_CLDOX Data Hold Time
T 31
t_CVCTX Control Inactive Delay^(b)
0
0
ns
0
12
0
10
ns
32
t_WLWH WR Pulse Width
2t_CLCL – 10 = 40
35
ns
33
t_WHLH WR Inactive to ALE High^(a)
t_CLCH – 2
t_CLCH – 2
ns
F ³⁴
t_WHDX Data Hold after WR^(a)
t_CLCL – 10 = 15
12
ns
65
t_AVWL A Address Valid to WR Low
t_CLCL+t_CHCL–1.25
t_CLCL+t_CHCL–1.25
ns
68
t_CHAV CLKOUTA High to A Address Valid
0
10
0
10
ns
87
t_AVBL A Address Valid to WHB, WLB Low t_CHCL–1.25
18
t_CHCL – 1.25
15
ns
A ^Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C_L=50 pF. For switching tests, V_IL=0.3 V and V_IH =V_CC–0.3 V.
a Testing is performed with equal loading on referenced pins.
D ^{R b This parameter applies to the DEN, WR, WHB and WLB signals.}
82
Am186^TMER and Am188^TMER Microcontrollers Data Sheet