AM186 Datasheet, PDF (69/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Numerical Key to Switching Parameter Symbols
Parameter
Number Symbol Description
Parameter
Number Symbol Description
1
t_DVCL Data in Setup
43
t_CLCH CLKOUTA Low Time
2
t_CLDX Data in Hold
44
t_CHCL CLKOUTA High Time
3
t_CHSV Status Active Delay
45
t_CH1CH2 CLKOUTA Rise Time
4
t_CLSH Status Inactive Delay
46
t_CL2CL1 CLKOUTA Fall Time
5
t_CLAV AD Address Valid Delay
47
t_SRYCL SRDY Transition Setup Time
6
t_CLAX Address Hold
48
t_CLSRY SRDY Transition Hold Time
7
t_CLDV Data Valid Delay
49
t_ARYCH ARDY Resolution Transition Setup Time
8
t_CHDX Status Hold Time
50
t_CLARX ARDY Active Hold Time
9
t_CHLH ALE Active Delay
51
t_ARYCHL ARDY Inactive Holding Time
10
t_LHLL ALE Width
52
t_ARYLCL ARDY Setup Time
11
t_CHLL ALE Inactive Delay
53
t_INVCH Peripheral Setup Time
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
t_AVLL AD Address Valid to ALE Low
t_LLAX AD Address Hold from ALE Inactive
t_AVCH AD Address Valid to Clock High
t_CLAZ AD Address Float Delay
t_CLCSV
t_CXCSX
MCS/PCS Active Delay
MCS/PCS Hold from Command
Inactive
t_CHCSX MCS/PCS Inactive Delay
t_DXDL DEN Inactive to DT/R Low
t_CVCTV Control Active Delay 1
t_CVDEX DEN Inactive Delay
t_CHCTV Control Active Delay 2
t_LHAV
t_AZRL
t_CLRL
t_RLRH
t_CLRH
R t_RHLH
t_RHAV
t_CLDOX
D^tCVCTX
ALE High to Address Valid
AD Address Float to RD Active
RD Active Delay
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High
RD Inactive to AD address Active
Data Hold Time
Control Inactive Delay
54
t_INVCL
55
t_CLTMV
57
t_RESIN
58
t_HVCL
59
t_RHDX
61
t_LOCK
62
t_CLHAV
A⁶³
t_CHCZ
64
t_CHCV
65
t_AVWL
66
t_AVRL
67
t_CHCSV
68
t_CHAV
69
t_CICOA
70
t_CICOB
71
t_CLEV
72
t_CLSL
75
t_DVSH
77
t_SHDX
78
t_SLDV
F ^{T DRQ Setup Time}
Timer Output Delay
RES Setup Time
HOLD Setup
RD High to Data Hold on AD Bus
Maximum PLL Lock Time
HLDA Valid Delay
Command Lines Float Delay
Command Lines Valid Delay (after Float)
A Address Valid to WR Low
A Address Valid to RD Low
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to Address Valid
X1 to CLKOUTA Skew
X1 to CLKOUTB Skew
CLKOUTA Low to SDEN Valid
CLKOUTA Low to SCLK Low
Data Valid to SCLK High
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
32
t_WLWH WR Pulse Width
79
t_CHRFD CLKOUTA High to RFSH Valid
33
t_WHLH WR Inactive to ALE High
80
t_CLCLX LCS Inactive Delay
34
t_WHDX Data Hold after WR
81
t_CLCSL LCS Active Delay
35
t_WHDEX WR Inactive to DEN Inactive
82
t_CLRF CLKOUTA High to RFSH Invalid
36
t_CKIN X1 Period
83
t_COAOB CLKOUTA to CLKOUTB Skew
37
t_CLCK X1 Low Time
84
t_LRLL LCS Precharge Pulse Width
38
t_CHCK X1 High Time
85
t_RFCY RFSH Cycle Time
39
t_CKHL X1 Fall Time
86
t_LCRF LCS Inactive to RFSH Active Delay
40
t_CKLH X1 Rise Time
87
t_AVBL A Address Valid to WHB, WLB Low
42
t_CLCL CLKOUTA Period
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
69