AM186 Datasheet, PDF (84/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Refresh Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
25 MHz
33 MHz
No. Symbol Description
Min
Max
Min
Max Unit
General Timing Responses
9
t_CHLH ALE Active Delay
20
15 ns
10
t_LHLL ALE Width
t_CLCL – 10 = 30
t_CLCL – 10 = 20
ns
11
t_CHLL ALE Inactive Delay
20
15 ns
Read/Write Cycle Timing Responses
25
t_CLRL RD Active Delay
0
20
0
15 ns
26
t_RLRH RD Pulse Width
2t_CLCL – 15 = 65
2t_CLCL – 15 = 45
ns
27
t_CLRH RD Inactive Delay
0
20
0
15 ns
28
t_RHLH RD Inactive to ALE High^(a)
t_CLCH – 3
t_CLCH – 3
ns
80
t_CLCLX LCS Inactive Delay
81
t_CLCSL LCS Active Delay
Refresh Timing Cycle Parameters
0
20
0
15 ns
0
20
0
15 ns
79
t_{CLRFD CLKOUTA Low to RFSH Valid}
82
t_{CLRF CLKOUTA High to RFSH Invalid}
T ⁸⁵
t_{RFCY RFSH Cycle Time}
86
t_{LCRF LCS Inactive to RFSH Active Delay}
0
20
0
15 ns
0
20
0
15 ns
6 x t_CLCL
2t_CLCL – 3
6 x t_CLCL
ns
2t_CLCL –3
ns
Notes:
All timing parameters are measured at V_CC/2 with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
F _{are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.}
D ^{R A a Testing is performed with equal loading on referenced pins.}
84
Am186^TMER and Am188^TMER Microcontrollers Data Sheet