AM186 Datasheet, PDF (30/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

PIN DESCRIPTIONS
Pins Used by Emulators
During a power-on reset, the address and data bus
The following pins are used by emulators: A19–A0,
AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the
Am186ER microcontroller), CLKOUTA, RFSH2/ADEN
(on the Am188ER microcontroller), RD, S2, S1/IMDIS,
S0/SREN, S6/CLKSEL1, and UZI/CLKSEL2.
pins (AD15–AD0 for the Am186ER microcontroller,
AO15–AO8 and AD7–AD0 for the Am188ER microcon-
troller) can also be used to load system configuration
information into the internal reset configuration regis-
ter. The system information is latched on the rising
edge of RES.
Emulators require that S6/CLKSEL1 and UZI/
CLKSEL2 be configured in their normal functionality,
AD15–AD8 (Am186™ER Microcontroller)
that is, as S6 and UZI. If BHE/ADEN (on the Am186ER Address and Data Bus (input/output, three-state,
microcontroller) or RFSH2/ADEN (on the Am188ER synchronous, level-sensitive)
microcontroller) is held Low during the rising edge of
RES, S6 and UZI are configured in their normal func-
tionality and cannot be programmed as PIOs.
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. AD15–
AD8 supply the high-order 8 bits of an address to the
A19–A0
system during the first period of a bus cycle (t₁). On a
(A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O ad-
dresses to the system one-half of a CLKOUTA period
earlier than the multiplexed address and data bus
(AD15–AD0 on the Am186ER microcontroller or
T ^{AO15–AO8 and AD7–AD0 on the Am188ER microcon-}
troller). During a bus hold or reset condition, the ad-
dress bus is in a high-impedance state.
AD7–AD0
F _{Address and Data Bus (input/output, three-state,}
synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. AD7–
A AD0 supply the low-order 8 bits of an address to the
system during the first period of a bus cycle (t₁). On a
write, these pins supply data to the system during the
remaining periods of that cycle (t₂, t₃, and t₄). On a
read, these pins latch data at the end of t₃.
R _{Also, if S0/SREN (show read enable) was pulled Low}
during reset or if the SR bit is set in the Internal Memory
Chip Select (IMCS) Register, these pins supply the
data read from internal memory during t₃ and t₄.
D On the Am186ER microcontroller, AD7–AD0 combine
write, these pins supply data to the system during the
remaining periods of that cycle (t₂, t₃, and t₄). On a
read, these pins latch data at the end of t₃.
Also, if S0/SREN (show read enable) was pulled Low
during reset or if the SR bit is set in the Internal Memory
Chip Select (IMCS) Register, these pins supply the
data read from internal memory during t₃ and t₄.
On the Am186ER microcontroller, AD15–AD8 combine
with AD7–AD0 to form a complete multiplexed address
and 16-bit data bus.
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is negated, these pins are three-stated during t₂,
t₃, and t_4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the Am186ER microcontroller,
AO15–AO8 and AD7–AD0 for the Am188ER microcon-
troller) can also be used to load system configuration
information into the internal reset configuration regis-
ter. The system information is latched on the rising
edge of RES.
AO15–AO8 (Am188™ER Microcontroller)
with AD15–AD8 to form a complete multiplexed ad- Address-Only Bus (output, three-state,
dress and 16-bit data bus.
synchronous, level-sensitive)
On the Am188ER microcontroller, AD7–AD0 combine
with AO15–AO8 to form a complete multiplexed ad-
dress bus while AD7–AD0 is the 8-bit data bus.
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WLB is negated, these pins are three-stated during t₂,
t₃, and t₄.
During a bus hold or reset condition, the address and
data bus are in a high-impedance state.
On the Am188ER microcontroller, the address-only
bus (AO15–AO8) contains valid high-order address bits
from bus cycles t₁–t₄. These outputs are three-stated
during a bus hold or reset.
On the Am188ER microcontroller, AO15–AO8 combine
with AD7–AD0 to form a complete multiplexed address
bus while AD7–AD0 is the 8-bit data bus.
On the Am188ER microcontroller during a power-on
reset, the AO15–AO8 and AD7–AD0 pins can also be
used to load system configuration information into an
internal register for later use.
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Am186^TMER and Am188^TMER Microcontrollers Data Sheet