AM186 Datasheet, PDF (35/112 Pages) Advanced Micro Devices – High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM

PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ER and Am188ER microcontrollers provide
32 individually programmable I/O pins. Each PIO can
be programmed with the following attributes: PIO func-
tion (enabled/disabled), direction (input/output), and
weak pullup or pulldown.
On the Am186ER and Am188ER microcontrollers, the
internal pullup resistor has a value of approximately
100 kohms. The internal pulldown resistor has a value
of approximately 100 kohms.
serted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via an RC network.
RFSH2/ADEN
(Am188™ER Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Asserted Low to signify a DRAM refresh bus
cycle. The use of RFSH2/ADEN to signal a refresh is
not valid when PSRAM mode is selected. Instead, the
MCS3/RFSH signal is provided to the PSRAM. During
reset, this pin is a pullup. This pin is three-stated during
bus holds and ONCE mode.
The pins that are multiplexed with PIO31–PIO0 are _{ADEN—If RFSH2/ADEN is held High or left floating on}
listed in Table 3 and Table 4 on page 36.
power-on reset, the AD bus (AO15–AO8 and AD7–AD0)
After power-on reset, the PIO pins default to various
is enabled or disabled during the address portion of LCS
configurations. The column titled Power-On Reset Sta-
tus in Table 3 and Table 4 lists the defaults for the PIOs.
The system initialization code must reconfigure any
PIOs as required.
If PIO29 (S6/CLKSEL1) is to be used in input mode, the
input device must not drive PIO29 Low during power-
on reset. The pin defaults to a PIO input with pullup, so
T _{it does not need to be driven High externally.}
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
F begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.
RD
A Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the microcontroller
is performing a memory or I/O read cycle. RD is guar-
anteed not to be asserted before the address and data
bus is floated during the address-to-data transition. RD
R _{is three-stated during bus holds and ONCE mode.}
RES
D ^{Reset (input, asynchronous, level-sensitive)}
and UCS bus cycles based on the DA bit in the LMCS
and UMCS registers. If the DA bit is set, the memory ad-
dress is accessed on the A19–A0 pins. This mode of op-
eration reduces power consumption. For more
information, see the Bus Operation section on page 41.
There is a weak internal pullup resistor on RFSH2/
ADEN so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data. Changing the DA
bit of the LMCS and UMCS registers will have no effect.
(S6 and UZI also assume their normal functionality in
this instance. The PIO Mode and Direction registers
cannot reconfigure these pins as PIOs. See Table 3
and Table 4 on page 36.) The pin is sampled within
three crystal clock cycles after the rising edge of RES.
RFSH2/ADEN is three-stated during bus holds and
ONCE mode.
Note: Once the above modes are set, they can be
changed only by resetting the processor.
RXD/PIO28
Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to the internal UART of the microcon-
troller.
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller immedi-
S2
ately terminates its present activity, clears its internal
logic, and CPU control is transferred to the reset ad-
dress FFFF0h.
Bus Cycle Status (output, three-state,
synchronous)
S2—This pin indicates to the system the type of bus
RES must be held Low for at least 1 ms.
cycle in progress. S2 can be used as a logical memory
RES can be asserted asynchronously to CLKOUTA be-
cause RES is synchronized internally. For proper initial-
ization, V_CC must be within specifications, and
CLKOUTA must be stable for more than four CLKOUTA
or I/O indicator. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, these pins are pullups. The S2–S0 pins are en-
coded as shown in Table 5 on page 37.
periods during which RES is asserted.
The microcontroller begins fetching instructions ap-
proximately 6.5 CLKOUTA periods after RES is deas-
Am186^TMER and Am188^TMER Microcontrollers Data Sheet
35