EP3SL50F780C4 Datasheet, PDF (311/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–301
Table 1–136. EP3SE260 Row Pins Input Timing Parameters (Part 2 of 3)
I/O Standard
DIFFERENTIAL
1.5-V
HSTL CLASS I
DIFFERENTIAL
1.5-V
HSTL CLASS II
DIFFERENTIAL
1.8-V
HSTL CLASS I
DIFFERENTIAL
1.8-V
HSTL CLASS II
DIFFERENTIAL
1.5-V
SSTL CLASS I
DIFFERENTIAL
1.5-V
SSTL CLASS II
DIFFERENTIAL
1.8-V
SSTL CLASS I
DIFFERENTIAL
1.8-V
SSTL CLASS II
DIFFERENTIAL
2.5-V
SSTL CLASS I
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
GCLK t_su
t_h
GCLK
PLL
t_su
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.160
1.297
1.041
-0.760
-1.160
1.297
1.041
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.240
1.393
1.047
-0.748
-1.240
1.393
1.047
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672 ns
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102 ns
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672 ns
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102 ns
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690 ns
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084 ns
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690 ns
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084 ns
t_h
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.760
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.160
1.297
1.041
-0.760
-1.160
1.297
1.041
-0.760
-1.169
1.306
1.032
-0.751
-0.748
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.240
1.393
1.047
-0.748
-1.240
1.393
1.047
-0.748
-1.249
1.402
1.038
-0.739
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672 ns
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102 ns
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672 ns
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102 ns
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690 ns
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084 ns
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690 ns
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084 ns
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 ns
2.121 2.156 2.341 2.250 2.701 2.186 2.369 2.250 2.701 ns
1.829 1.945 2.171 2.052 2.073 1.954 2.182 2.052 2.073 ns
-1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2