EP3SL50F780C4 Datasheet, PDF (175/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–165
Table 1–86 lists the EP3SL200 row pins input timing parameters for differential I/O
standards.
Table 1–86. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 2)
I/O Standard Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
LVDS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
MINI-LVDS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
RSDS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
DIFFERENTIAL PLL _th
1.2-V
HSTL CLASS I _GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
DIFFERENTIAL PLL _th
1.5-V
HSTL CLASS I _GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.137
1.274
1.064
-0.783
-1.137
1.274
1.064
-0.783
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.216
1.369
1.071
-0.772
-1.216
1.369
1.071
-0.772
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526 ns
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297 ns
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526 ns
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297 ns
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526 ns
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297 ns
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656 ns
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118 ns
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656 ns
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118 ns
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672 ns
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102 ns
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672 ns
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102 ns
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2