EP3SL50F780C4 Datasheet, PDF (134/341 Pages) Altera Corporation – Stratix III Device Handbook

1–124
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–72. EP3SL150 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
GCLK ^tsu
1.2-V HSTL
t_h
CLASS I
GCLK ^tsu
PLL _th
GCLK ^tsu
1.2-V HSTL
t_h
CLASS II
GCLK ^tsu
PLL _th
3.0-V PCI
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
3.0-V
PCI-X
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
-0.830
-0.877 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 ns
0.946
1.008 1.426 1.556 1.558 1.612 1.831 1.558 1.566 1.627 1.875 ns
1.083
1.089 1.754 1.986 2.221 2.102 2.045 2.003 2.237 2.115 2.092 ns
-0.831
-0.821 -1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 ns
-0.830
-0.877 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 ns
0.946
1.008 1.426 1.556 1.558 1.612 1.831 1.558 1.566 1.627 1.875 ns
1.083
1.089 1.754 1.986 2.221 2.102 2.045 2.003 2.237 2.115 2.092 ns
-0.831
-0.821 -1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 ns
-0.931
-0.975 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns
1.046
1.105 1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217 ns
0.982
0.998 1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843 ns
-0.731
-0.730 -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 ns
-0.931
-0.975 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns
1.046
1.105 1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217 ns
0.982
0.998 1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843 ns
-0.731
-0.730 -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 ns
Table 1–73 lists the EP3SL150 column pins output timing parameters for single-ended
I/O standards.
Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part 1 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.422
4mA
GCLK
PLL ^tco
3.898
3.439
3.841
4.768 5.127 5.625 5.473 5.808 5.127 5.625 5.473 5.808 ns
5.355 5.880 6.341 6.161 6.543 5.880 6.341 6.161 6.543 ns
3.3-V
LVTTL
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.355
3.781
3.269
3.692
3.372
3.774
3.286
3.688
4.659 5.016 5.512 5.360 5.695 5.016 5.512 5.360 5.695 ns
5.246 5.718 6.228 6.048 6.430 5.718 6.228 6.048 6.430 ns
4.555 4.918 5.420 5.268 5.603 4.918 5.420 5.268 5.603 ns
5.142 5.583 6.136 5.956 6.338 5.583 6.136 5.956 6.338 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.262
3.685
3.279
3.681
4.538 4.890 5.379 5.227 5.562 4.890 5.379 5.227 5.562 ns
5.125 5.555 6.095 5.915 6.297 5.555 6.095 5.915 6.297 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation