EP3SL50F780C4 Datasheet, PDF (229/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–219
Table 1–105. EP3SE50 Column Pins Input Timing Parameters (Part 3 of 3)
I/O Standard
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.730
0.848
1.120
-0.867
-0.738
0.856
1.112
-0.859
-0.751
0.884
1.138
-0.870
-0.763
0.896
1.126
-0.858
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835 ns
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193 ns
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850 ns
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178 ns
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
Table 1–106 lists the EP3SE50 row pins input timing parameters for differential I/O
standards.
Table 1–106. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 3)
I/O Standard
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
DIFFERENTIAL
1.2-V HSTL
CLASS II
Clock
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su -0.925
t_h 1.048
t_su 0.886
t_h -0.626
t_su -0.925
t_h 1.048
t_su 0.886
t_h -0.626
t_su -0.925
t_h 1.048
t_su 0.886
t_h -0.626
t_su -0.740
t_h 0.856
t_su 1.081
t_h -0.828
t_su -0.740
t_h 0.856
t_su 1.081
t_h -0.828
-0.948
1.086
0.901
-0.628
-0.948
1.086
0.901
-0.628
-0.948
1.086
0.901
-0.628
-0.773
0.902
1.086
-0.822
-0.773
0.902
1.086
-0.822
-1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 ns
1.223 1.219 1.381 1.322 1.601 1.199 1.353 1.296 1.634 ns
1.866 2.244 2.450 2.324 2.344 2.289 2.502 2.376 2.396 ns
-1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 ns
-1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 ns
1.223 1.219 1.381 1.322 1.601 1.199 1.353 1.296 1.634 ns
1.866 2.244 2.450 2.324 2.344 2.289 2.502 2.376 2.396 ns
-1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 ns
-1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 ns
1.223 1.219 1.381 1.322 1.601 1.199 1.353 1.296 1.634 ns
1.866 2.244 2.450 2.324 2.344 2.289 2.502 2.376 2.396 ns
-1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 ns
-1.101 -1.201 -1.301 -1.251 -1.526 -1.210 -1.307 -1.259 -1.563 ns
1.288 1.408 1.531 1.467 1.741 1.427 1.548 1.486 1.779 ns
1.779 2.020 2.261 2.140 2.165 2.022 2.265 2.144 2.212 ns
-1.377 -1.571 -1.757 -1.668 -1.687 -1.564 -1.752 -1.662 -1.732 ns
-1.101 -1.201 -1.301 -1.251 -1.526 -1.210 -1.307 -1.259 -1.563 ns
1.288 1.408 1.531 1.467 1.741 1.427 1.548 1.486 1.779 ns
1.779 2.020 2.261 2.140 2.165 2.022 2.265 2.144 2.212 ns
-1.377 -1.571 -1.757 -1.668 -1.687 -1.564 -1.752 -1.662 -1.732 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2