EP3SL50F780C4 Datasheet, PDF (30/341 Pages) Altera Corporation – Stratix III Device Handbook

1–20
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–22. TriMatrix Memory Block Performance Specifications for Stratix III Devices (Note 1) (Part 3 of 3)
Memory
Block
Type
Mode
ALUTs
TriMatrix
Memory
C2 (6)
V_CCL =
1.1 V
C3 C4
C4L
V_CCL = V_CCL = V_CCL = V_CCL =
1.1 V 1.1 V 1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4 I4L
V_CCL= V_CCL= ^Unit
1.1 V 0.9 V
Simple dual-port 2K × 64 (with ECC) 0
1
255 210 180 180 130 195 180 120 MHz
M144K
(3), (5)
Min Pulse Width (Clock High Time)
—
—
800 1000 1100 1100 1800 1000 1100 1800 ps
Min Pulse Width (Clock Low Time)
—
—
500 625 690 690 1100 625 690 1100 ps
Notes to Table 1–22:
(1) Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block
performance. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) The F_max shown for M9K degrades 2% when you use the Error Detection CRC feature on the device, except for the C4L speed grade with V_CCL = 0.9 V. For the
C4L speed grade with V_CCL = 0.9V, there is no degradation in F_max when you use the Error Detection CRC feature.
(3) The F_max shown for M144K degrades 10 MHz when you use byte-enable support on M144K.
(4) F_max is applicable when the COMPTABILITY option is turned ON.
(5) F_max is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in Quartus II software.
(6) The F_max for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table.
Configuration and JTAG Specifications
Table 1–23 lists the Stratix III configuration mode specifications.
Table 1–23. Configuration Mode Specifications for Stratix III Devices (Note 1)
Passive Serial
Programming Mode
DCLK F_max
Unit
100
MHz
Fast Passive Parallel (2)
100
MHz
Fast Active Serial (3)
40
MHz
Notes to Table 1–23:
(1) DCLK F_max is restricted when you enable the Remote Update feature. For more information, refer to the Remote
Update Circuitry (ALTREMOTE_UPDATE) Megafunction User Guide.
(2) The data rate must be 4× slower than the clock when you use decompression and/or encryption.
(3) For more information about the minimum and typical DCLK F_max value in Fast Active Serial configuration, refer to
the Configuring Stratix III Devices chapter.
Table 1–24 lists the JTAG timing parameters and values for Stratix III devices. Refer to
the figure for “HIGH-SPEED I/O Block” in the “Glossary” on page 1–326 for the
JTAG timing requirements.
Table 1–24. JTAG Timing Parameters and Values for Stratix III Devices
Symbol
Parameter
Min
Max
Unit
t_JCP
TCK clock period
30
—
ns
t_JCH
TCK clock high time
14
—
ns
t_JCL
TCK clock low time
14
—
ns
t_JPSU (TDI)
JTAG port setup time for TDI
1
—
ns
t_JPSU (TMS)
JTAG port setup time for TMS
3
—
ns
t_JPH
JTAG port hold time
5
—
ns
t_JPCO
JTAG port clock to output
—
11
ns
t_JPZX
JTAG port high impedance to valid output
—
14
ns
t_JPXZ
JTAG port valid output to high impedance
—
14
ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation