EP3SL50F780C4 Datasheet, PDF (245/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–235
Table 1–113. EP3SE80 Column Pins Output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA
GCLK
PLL
t_co
3.412
3.737
3.412
3.743
4.773 5.155 5.503 5.551 5.728 5.155 5.503 5.551 5.728 ns
5.265 5.694 6.260 6.076 6.494 5.694 6.260 6.076 6.494 ns
3.0-V
LVCMOS
GCLK t_co
8mA
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
3.275
3.658
3.245
3.653
3.275
3.664
3.245
3.659
4.578 4.956 5.368 5.369 5.593 4.956 5.368 5.369 5.593 ns
5.141 5.565 6.125 5.941 6.359 5.565 6.125 5.941 6.359 ns
4.532 4.904 5.359 5.300 5.586 4.904 5.359 5.300 5.586 ns
5.134 5.558 6.117 5.931 6.352 5.558 6.117 5.931 6.352 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.223
3.644
3.224
3.650
4.510 4.883 5.344 5.299 5.571 4.883 5.344 5.299 5.571 ns
5.120 5.543 6.102 5.916 6.337 5.543 6.102 5.916 6.337 ns
GCLK t_co
4mA
GCLK
PLL
t_co
3.559
3.859
3.559
3.865
5.027 5.434 5.750 5.833 5.976 5.434 5.750 5.833 5.976 ns
5.472 5.921 6.507 6.323 6.742 5.921 6.507 6.323 6.742 ns
GCLK t_co 3.434
3.434 4.854 5.250 5.618 5.636 5.843 5.250 5.618 5.636 5.843 ns
8mA
GCLK
PLL
t_co
3.759
3.765 5.353 5.795 6.375 6.191 6.609 5.795 6.375 6.191 6.609 ns
2.5 V
GCLK t_co 3.334
3.334 4.725 5.114 5.522 5.496 5.749 5.114 5.522 5.496 5.749 ns
12mA
GCLK
PLL
t_co
3.715
3.721 5.266 5.704 6.280 6.094 6.515 5.704 6.280 6.094 6.515 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.307
3.677
3.307
3.683
4.656 5.047 5.479 5.446 5.706 5.047 5.479 5.446 5.706 ns
5.227 5.662 6.237 6.051 6.472 5.662 6.237 6.051 6.472 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2