EP3SL50F780C4 Datasheet, PDF (18/341 Pages) Altera Corporation – Stratix III Device Handbook

1–8
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–9. On-Chip Termination Variation after Power-up Calibration (Note 1)
Symbol
Description
dR/dV
OCT variation with voltage without re-calibration
dR/dT
OCT variation with temperature without re-calibration
Note to Table 1–9:
(1) Valid for V_CCIO range of ± 5% and temperature range of 0° to 85° C.
V_CCIO (V)
3
2.5
1.8
1.5
1.2
3
2.5
1.8
1.5
1.2
Commercial
Typical
0.029
0.036
0.065
0.104
0.177
0.294
0.301
0.355
0.344
0.348
Unit
%/mV
%/mV
%/mV
%/mV
%/mV
%/°C
%/°C
%/°C
%/°C
%/°C
Pin Capacitance
Table 1–10 lists the Stratix III device family pin capacitance.
s
Table 1–10. Pin Capacitance for Stratix III Device Family
Symbol
Parameter
Typical Unit
C_IOTB
C_IOLR
C_CLKTB
Input capacitance on top and bottom I/O pins
4
pF
Input capacitance on left and right I/O pins
4
pF
Input capacitance on top and bottom
non-dedicated clock input pins
4
pF
C_CLKLR
Input capacitance on left and right
non-dedicated clock input pins
4
pF
C_OUTFB
Input capacitance on dual-purpose clock
output and feedback pins
5
pF
C_CLK1, C_CLK3, C , _CLK8 and Input capacitance for dedicated clock input
C_CLK10
pins
2
pF
Hot-Socketing
Table 1–11 lists the hot-socketing specifications for Stratix III devices.
Table 1–11. Hot-Socketing Specifications for Stratix III Devices
Symbol
Parameter
Maximum
|I_IOPIN|(DC)
DC current per I/O pin
300 A
|I_IOPIN|(AC)
AC current per I/O pin
8 mA (1)
Note to Table 1–11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is I/O pin
capacitance and dv/dt is the slew rate.
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation