EP3SL50F780C4 Datasheet, PDF (276/341 Pages) Altera Corporation – Stratix III Device Handbook

1–266
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–123. EP3SE110 Column Pins Output Timing Parameters (Part 6 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
V_CCL=
1.1 V 0.9 V
UnitS
GCLK t_co
4mA
GCLK
PLL
t_co
3.328
3.707
3.328
3.720
4.681 5.069 5.545 5.410 5.722 5.069 5.545 5.410 5.722 ns
5.266 5.691 6.301 6.137 6.539 5.691 6.301 6.137 6.539 ns
GCLK t_co
6mA
GCLK
PLL
t_co
3.321
3.701
3.321
3.713
4.679 5.067 5.544 5.409 5.721 5.067 5.544 5.409 5.721 ns
5.264 5.691 6.300 6.136 6.538 5.691 6.300 6.136 6.538 ns
1.8-V
HSTL
CLASS I
GCLK t_co
8mA
GCLK
PLL
t_co
3.313
3.693
3.313
3.705
4.671 5.060 5.537 5.402 5.714 5.060 5.537 5.402 5.714 ns
5.257 5.683 6.293 6.129 6.531 5.683 6.293 6.129 6.531 ns
GCLK t_co
10mA
GCLK
PLL
t_co
3.316
3.695
3.316
3.708
4.674 5.063 5.541 5.406 5.718 5.063 5.541 5.406 5.718 ns
5.260 5.686 6.297 6.133 6.535 5.686 6.297 6.133 6.535 ns
GCLK t_co
12mA
GCLK
PLL
t_co
3.313
3.692
3.313
3.705
4.677 5.067 5.545 5.410 5.722 5.067 5.545 5.410 5.722 ns
5.262 5.689 6.301 6.137 6.539 5.689 6.301 6.137 6.539 ns
1.8-V
HSTL
CLASS II
GCLK t_co
16mA
GCLK
PLL
t_co
3.321
3.700
3.321
3.713
4.676 5.064 5.541 5.406 5.718 5.064 5.541 5.406 5.718 ns
5.261 5.687 6.297 6.133 6.535 5.687 6.297 6.133 6.535 ns
GCLK t_co
4mA
GCLK
PLL
t_co
3.333
3.712
3.333
3.725
4.689 5.079 5.556 5.421 5.733 5.079 5.556 5.421 5.733 ns
5.275 5.701 6.312 6.148 6.550 5.701 6.312 6.148 6.550 ns
GCLK t_co
6mA
GCLK
PLL
t_co
3.329
3.708
3.329
3.721
4.690 5.080 5.559 5.424 5.736 5.080 5.559 5.424 5.736 ns
5.276 5.704 6.315 6.151 6.553 5.704 6.315 6.151 6.553 ns
1.5-V
HSTL
CLASS I
GCLK t_co
8mA
GCLK
PLL
t_co
3.325
3.704
3.325
3.717
4.686 5.076 5.554 5.419 5.731 5.076 5.554 5.419 5.731 ns
5.271 5.699 6.310 6.146 6.548 5.699 6.310 6.146 6.548 ns
GCLK t_co
10mA
GCLK
PLL
t_co
3.318
3.697
3.318
3.710
4.679 5.069 5.547 5.412 5.724 5.069 5.547 5.412 5.724 ns
5.264 5.692 6.303 6.139 6.541 5.692 6.303 6.139 6.541 ns
GCLK t_co
12mA
GCLK
PLL
t_co
3.319
3.697
3.319
3.711
4.686 5.077 5.557 5.422 5.734 5.077 5.557 5.422 5.734 ns
5.271 5.699 6.313 6.149 6.551 5.699 6.313 6.149 6.551 ns
1.5-V
HSTL
CLASS II
GCLK t_co
16mA
GCLK
PLL
t_co
3.317
3.695
3.317
3.709
4.667 5.055 5.531 5.396 5.708 5.055 5.531 5.396 5.708 ns
5.252 5.677 6.287 6.123 6.525 5.677 6.287 6.123 6.525 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation