EP3SL50F780C4 Datasheet, PDF (132/341 Pages) Altera Corporation – Stratix III Device Handbook

1–122
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–72 lists the EP3SL150 row pins input timing parameters for single-ended I/O
standards.
Table 1–72. EP3SL150 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
GCLK ^tsu
t_h
3.3-V LVTTL
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
3.0-V LVTTL
GCLK ^tsu
PLL _th
3.0-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
2.5 V
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
1.8 V
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
1.5 V
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
1.2 V
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
-0.925
-0.964 -1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993 ns
1.040
1.094 1.544 1.677 1.910 1.851 2.173 1.698 1.917 1.860 2.212 ns
0.988
1.009 1.642 1.858 1.971 1.855 1.796 1.865 1.993 1.875 1.848 ns
-0.737
-0.741 -1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363 ns
-0.925
-0.964 -1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993 ns
1.040
1.094 1.544 1.677 1.910 1.851 2.173 1.698 1.917 1.860 2.212 ns
0.988
1.009 1.642 1.858 1.971 1.855 1.796 1.865 1.993 1.875 1.848 ns
-0.737
-0.741 -1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363 ns
-0.931
-0.975 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns
1.046
1.105 1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217 ns
0.982
0.998 1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843 ns
-0.731
-0.730 -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 ns
-0.931
-0.975 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns
1.046
1.105 1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217 ns
0.982
0.998 1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843 ns
-0.731
-0.730 -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 ns
-0.919
-0.968 -1.366 -1.484 -1.700 -1.651 -1.972 -1.488 -1.694 -1.649 -2.008 ns
1.034
1.098 1.550 1.691 1.928 1.869 2.191 1.706 1.932 1.875 2.227 ns
0.994
1.005 1.636 1.844 1.953 1.837 1.778 1.857 1.978 1.860 1.833 ns
-0.743
-0.737 -1.235 -1.393 -1.453 -1.365 -1.296 -1.399 -1.467 -1.378 -1.348 ns
-0.949
-1.000 -1.406 -1.530 -1.590 -1.662 -1.875 -1.521 -1.582 -1.663 -1.913 ns
1.065
1.131 1.590 1.738 1.824 1.880 2.098 1.739 1.826 1.889 2.137 ns
0.964
0.966 1.589 1.806 1.955 1.835 1.780 1.824 1.977 1.854 1.832 ns
-0.712
-0.698 -1.190 -1.356 -1.455 -1.362 -1.298 -1.366 -1.466 -1.372 -1.347 ns
-0.939
-0.989 -1.382 -1.498 -1.522 -1.594 -1.807 -1.490 -1.517 -1.598 -1.848 ns
1.055
1.120 1.566 1.706 1.756 1.812 2.030 1.708 1.761 1.824 2.072 ns
0.974
0.977 1.613 1.838 2.023 1.903 1.848 1.855 2.042 1.919 1.897 ns
-0.722
-0.709 -1.214 -1.388 -1.523 -1.430 -1.366 -1.397 -1.531 -1.437 -1.412 ns
-0.879
-0.936 -1.303 -1.397 -1.363 -1.435 -1.648 -1.394 -1.362 -1.443 -1.693 ns
0.995
1.067 1.487 1.605 1.597 1.653 1.871 1.612 1.606 1.669 1.917 ns
1.034
1.030 1.692 1.939 2.182 2.062 2.007 1.951 2.197 2.074 2.052 ns
-0.782
-0.762 -1.293 -1.489 -1.682 -1.589 -1.525 -1.493 -1.686 -1.592 -1.567 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation